PI6C110EV データシートの表示（PDF） - Pericom Semiconductor
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PI6C110EV Datasheet PDF : 15 Pages
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PI6C110E
Clock Solution for 133 MHz
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0ns
1
VCO Internal
25ns
50ns
2
75ns
Center
CPU
3V66
PCI 33 MHz
APIC 33MHz
PWRDWN#
SDRAM
REF 14.318 MHz
48 MHz
PWRDWN# Timing Diagram
Notes:
1. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest should be held LOW on the
next high to low transition.
2. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside the part.
3. The shaded sections on the SDRAM, REF, and 48 MHz clocks indicate dont care states.
4. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66/133 MHz.
Minimum and Maximum Lumped Capacitive Loads
Clock
Min.
Load
Max.
Load
Units
Notes
CPU
10
20
1 device load, possible 2 loads
PCI
10
30
Must meet PCI 2.1 requirements
SDRAM 20
30
PC100/PC133 specs
3V66
10
30
pF 1 device load, possible 2 loads
48MHz
10
20
1 device load,
REF
10
20
1 device load,
APIC
10
20
1 device load,
11
PS8410
08/11/99
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