TC58NVG1S3BFT00 データシートの表示（PDF） - Toshiba

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TC58NVG1S3BFT00

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

Toshiba 

TC58NVG1S3BFT00/TC58NVG1S8BFT00

(10) Note regarding the WP signal

The Erase and Program operations are automatically reset when WP goes Low. The operations are

enabled and disabled as follows:

Enable Programming

WE

DIN

80

10

WP

RY / BY

tWW (100 ns MIN)

Disable Programming

WE

DIN

80

10

WP

RY / BY

tWW (100 ns MIN)

Enable Erasing

WE

DIN

60

D0

WP

RY / BY

tWW (100 ns MIN)

Disable Erasing

WE

DIN

60

D0

WP

RY / BY

tWW (100 ns MIN)

31

2003-10-30A

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