TC35273 データシートの表示（PDF） - Toshiba

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TC35273

TOSHIBA MPEG-4 Audiovisual LSI

Toshiba 

Preliminary

MPEG-4 Audiovisual Codec LSI

TC35273

/HCS

HADDR

/HWR

/HWAIT

HDAT

(a)

TCSS

TADS

TWTAD

TWTID

TDTWS

(b)

(c)

TCSH

TADH

TRDH

TRR

TDTID

Fig. 4 Write Operation in handshake mode

3.1.2 Synchronized access mode

In this mode, a host CPU accomplishes an access to TC35273 in the specified period without a

handshake. However, when the host CPU accesses to the embedded DRAM in TC35273, it has to

check whether the next access is available or not by checking a status register before the access.

Fig.5 shows the timing diagram of a read operation. A read access starts by asserting both a chip

select signal (/HCS) and a read signal (/RD) (timing (a)). After the specified cycles indicated as Tacs,

the host CPU gets the read data and finishes the read operation by negating both /HCS and /HRD

(timing (b)).

Fig.6 shows the timing diagram of a write operation. A write access starts by asserting both /HCS

and a write signal (/WR) (timing (a)). After the specified cycles, the host CPU finishes the write

operation by negating both /HCS and /HWR (timing (b)).

TOSHIBA Confidential

11/23

Version 0.90

2000-4-27

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