TC35273 データシートの表示（PDF） - Toshiba

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TC35273

TOSHIBA MPEG-4 Audiovisual LSI

Toshiba 

Preliminary

MPEG-4 Audiovisual Codec LSI

TC35273

3.1.3 Interrupt

An interrupt to the external host CPU is performed as follows.

(a) HINT Active

When an interrupt is requested by TC35273, HINT becomes high (timing (a)).

(b) Clear HINT

The host CPU detects the interrupt request by HINT. The CPU also detects the interrupt

causes by reading an interrupt status register in the host interface of TC35273. When the CPU

reads the register at the timing (b), The CPU detects the interrupt causes occurring during the

timing (a) and (b). HINT is cleared when the CPU reads the interrupt status register.

(c) Multiple Interrupt

Even if another interrupt is requested during the timing (b) and (c), The assertion of HINT is

suspended to the timing (c).

HINT

/HCS

HADDR

/HRD

/H W A IT

H D AT

(a)

(b)

(c)

TRRD

TACS

Fig. 7 Interrupt Operation

TOSHIBA Confidential

13/23

Version 0.90

2000-4-27

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