Philips Semiconductors
Camera Digital Signal Processor
(CAMDSP)
SSG TIMING
Clock count for NTSC and PAL mode
Preliminary specification
SAA9750H
handbook, full pageCwCidtDh 510H
0
−10 (−15)
SHD
50 (45)
1H
606 (618) clocks
596 (603)
60 (60)
HD
CP2
,, ,, ,,,,, Y0toY7
,, ,, ,,,,, HSYNC
,,,,,, ,,,,,,,,,,,,,, YDAandCDA
24 (24)
33 (33)
48 (48)
57 (57)
62 (62)
75 (75)
139 (151)
93 (93)
165 (177)
107 (107)
SYNC
CCD 670H 0
SHD
80 (80)
1H
806 (824) clocks
80 (80)
HD
CP2
Y0 to Y7
32 (32)
,,28 (28)
48 (48)
,,, HSYNC
YDA and CDA
51 (51)
100 (100)
108 (108)
,,,,,,, 168 (184)
,,,,,, 195 (203)
SYNC
61 (61)
121 (121)
MHA307
1996 Feb 16
Fig.5 SSG timing (continued in Fig.6).
11