SAA9750H データシートの表示（PDF） - Philips Electronics

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SAA9750H

Camera Digital Signal Processor (CAMDSP)

Philips Electronics 

Philips Semiconductors

Camera Digital Signal Processor

(CAMDSP)

Preliminary specification

SAA9750H

Clock

Table 1 Clock frequency

NTSC

MODE

PAL

SECAM

510H

670H

720H

768H

510H

670H

720H

768H

CCD

CLK1 (MHz)

9.5350

12.7132

13.5000

14.3182

9.6563

12.8750

13.5000

14.1875

CLK2 (MHz)

19.0699

−

−

−

19.3125

−

−

−

Table 2 Clock used for each block

MODE

SSG BLOCK

510H NTSC/PAL CLK1

Other modes

CLK1

Y/C BLOCK

CLK1

CLK1

ENCODER

BLOCK

CLK1 and CLK2

(upsampling)

CLK1

Y-DAC BLOCK C-DAC BLOCK

CLK1

CLK2

CLK1

CLK1

MICROPROCESSOR INTERFACE FORMAT

handbook, full pageCwSidth

CK

DI

MSB

LSB MSB

LSB MSB

slave address(1)

subaddress

data

LSB

MHA304

(1) Slave address 001.

1996 Feb 16

Fig.7 Microprocessor interface format.

13

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