STLC2411 データシートの表示（PDF） - STMicroelectronics

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STLC2411

BLUETOOTH™ BASEBAND

STMicroelectronics 

STLC2411

Table 9. STLC2411 Pin List (continued)

Name Pin #

Description

DIR PU/PD VDD

PAD

uart2_rxd G3 Uart2 receive data

I

(2)

V1

CMOS, 3.3V TTL

compatible

I2C interface

i2c_dat

i2c_clk

C1 I2C data pin

D3 I2C clock pin

I/O

(3)

V1 CMOS, 3.3V TTL

compatible, 2mA

I/O

(3)

V1

tri-state

slew rate control

USB interface

usb_dn

G1 USB - pin (Needs a series resistor of 27 Ω ±5%) I/O

(1)

V1

usb_dp

G2 USB + pin (Needs a series resistor of 27 Ω ±5%) I/O

(1)

V1

GPIO interface

gpio0

gpio1

gpio2

F14 Gpio port 0

F13 Gpio port 1

F12 Gpio port 2

I/O

PU

CMOS, 3.3V TTL

compatible, 4mA

I/O

PU

V1

tri-state

I/O

PU

slew rate control

gpio3

E14 Gpio port 3

I/O

PU

CMOS, 3.3V TTL

compatible, 4mA

V1

tri-state

slew rate control

schmitt trigger

gpio4

gpio5

gpio6

gpio7

E13 Gpio port 4

E12 Gpio port 5

D13 Gpio port 6

D12 Gpio port 7

I/O

PU

CMOS, 3.3V TTL

I/O

I/O

PU

PU

V1

compatible, 4mA

tri-state

slew rate control

I/O

PU

gpio8

C14 Gpio port 8

I/O

PU

gpio9

A14 Gpio port 9

I/O

PU

gpio10

gpio11

gpio12

gpio13

B13 Gpio port 10

A13 Gpio port 11

C12 Gpio port 12

B12 Gpio port 13

I/O

PU

CMOS, 3.3V TTL

I/O

I/O

PU

PU

V1

compatible, 2mA

tri-state

slew rate control

I/O

PU

gpio14

A12 Gpio port 14

I/O

PU

gpio15

C11 Gpio port 15

I/O

PU

Clock and test pins

xin

nreset

A1 System clock

B2 Reset

I

CMOS, 3.3V TTL

I

V1

compatible

schmitt trigger

sys_clk_req B1 System clock request

I/O

CMOS, 3.3V TTL

V1

compatible, 2mA

tri-state

slew rate control

lpo_clk_p G13 Low power oscillator + / Slow clock input

lpo_clk_n G12 Low power oscillator -

I

(1)

V2

O

8/25

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