SIP11203DB データシートの表示（PDF） - Vishay Semiconductors

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SIP11203DB

SiP11203 Demonstration Board

Vishay Semiconductors 

SiP11203DB

Vishay Siliconix

DEMONSTRATION BOARD INFORMATION

The demonstration board is an 8-layer board in the

eighth-brick form factor, manufactured in 2 oz copper.

The circuit schematics for the SiP11203 demonstration

board are illustrated in Figure 2 and Figure 3.

Power Conversion Circuit

The primary power circuit is a half-bridge configuration

with a 4:1 turns ratio transformer, T2, connected

between the switching pole of the half-bridge and the

center tap of the capacitive input filter. The half-bridge

capacitors C10 to C17 are configured as two series-con-

nected banks of four parallel-connected 1 µF ceramic

capacitors. Resistors R20 and R21 provide voltage bal-

ancing and discharge paths for the capacitor banks. The

primary side half-bridge circuit is driven using the Si9122

controller IC. This generates both the primary MOSFET

drive signals as well as the timing signals for the second-

ary side synchronous MOSFETs. These timing signals,

SRL and SRH, are coupled to the secondary through the

pulse transformer T1. The SiP11203 uses the timing

information to drive the secondary synchronous MOS-

FETs Q3 to Q6. The secondary side synchronous MOS-

FETs rectify the center-tapped transformer secondary

voltage, the output of which is filtered by the LC-filter L1-

C28-C31. L1 is a 900 nH inductor, C28 is a 22 µF tantalum

capacitor and C31 is a 100 µF ceramic capacitor.

RCD snubbers are placed across the synchronous rec-

tifier MOSFETs in order to clamp the secondary leakage

inductance voltage spike and reduce switching losses.

Some of the main switching circuit waveforms are plot-

ted in Figure 4. The converter efficiency over the line

and load range is depicted in Figure 5. Note that these

efficiency readings do not take account of the voltage

drops across the plug-in pins of the demonstration

board.

Bias Supply

The primary bias supply, VCC, is a 10.4 V supply that is

generated from an auxiliary winding, L1-B of the output

filter inductor. The auxiliary winding turns ratio is

3.333:1, resulting in an auxiliary winding voltage of

approximately 11 V during the inductor current ramp-

down period. This voltage is rectified and filtered by

diode D4 and capacitors C23 and C26. During startup

and other conditions such as short-circuited output, the

primary bias voltage is supplied by means of a 9.1 V lin-

ear pre-regulator on the Si9122 controller. An external

PNP pre-regulator transistor Q8 is provided to divert the

main power dissipation away from the Si9122 during the

period when the 9.1 V bias is being utilised. The rise of

VCC and VO during startup is depicted in Figure 6 (a). It

is clear that converter operation commences when VCC

reaches 9.1 V and, the change to the auxiliary bias level

can also be seen.

www.vishay.com

2

Figure 2. SiP11203 Demonstration Board Primary Side Schematic

Document Number: 74254

S-60997–Rev. A, 12-Jun-06

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