RTL8130 データシートの表示（PDF） - Realtek Semiconductor

部品番号

コンポーネント説明

一致するリスト

RTL8130

REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH MII & AUI INTERFACE

Realtek Semiconductor 

RTL8130 Preliminary

5. Register Descriptions

The RTL8130 provides the following set of operational registers mapped into PCI memory space or I/O

space.

Offset

0000h

0001h

0002h

0003h

0004h

0005h

0006h-0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h-0013h

0014h-0017h

0018h-001Bh

001Ch-001Fh

0020h-0023h

0024h-0027h

0028h-002Bh

002Ch-002Fh

0030h-0033h

0034h-0035h

0036h

0037h

0038h-0039h

003Ah-003Bh

003Ch-003Dh

003Eh-003Fh

0040h-0043h

0044h-0047h

0048h-004Bh

R/W

R/W

R/W

R/W

R/W

R/W

R/W

-

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R

R/W

R/W

R

R/W

R/W

R/W

R/W

R/W

004Ch-004Fh

R/W

0050h

R/W

0051h

R/W

0052h

R/W

Tag

IDR0

IDR1

IDR2

IDR3

IDR4

IDR5

-

MAR0

MAR1

MAR2

MAR3

MAR4

MAR5

MAR6

MAR7

TSD0

TSD1

TSD2

TSD3

TSAD0

TSAD1

TSAD2

TSAD3

RBSTART

ERBCR

ERSR

CR

CAPR

CBR

IMR

ISR

TCR

RCR

TCTR

MPC

9346CR

CONFIG0

CONFIG1

Description

ID Register 0, The ID register0-5 are only permitted to read/write by

4-bye access.

ID Register 1

ID Register 2

ID Register 3

ID Register 4

ID Register 5

Reserved

Multicast Register 0, The MAR register0-7 are only permitted to

read/write by 4-bye access.

Multicast Register 1

Multicast Register 2

Multicast Register 3

Multicast Register 4

Multicast Register 5

Multicast Register 6

Multicast Register 7

Transmit Status of Descriptor 0

Transmit Status of Descriptor 1

Transmit Status of Descriptor 2

Transmit Status of Descriptor 3

Transmit Start Address of Descriptor0

Transmit Start Address of Descriptor1

Transmit Start Address of Descriptor2

Transmit Start Address of Descriptor3

Receive (Rx) Buffer Start Address

Early Receive (Rx) Byte Count Register

Early Rx Status Register

Command Register

Current Address of Packet Read

Current Buffer Address: The initial value is 0000h. It reflects total

received byte-count in the rx buffer.

Interrupt Mask Register

Interrupt Status Register

Transmit (Tx) Configuration Register

Receive (Rx) Configuration Register

Timer CounT Register: This register contains a 32-bit general-

purpose timer. Writing any value to this 32-bit register will reset the

original timer and begin to count from zero.

Missed Packet Counter: Indicates the number of packets discarded

due to rx FIFO overflow. It is a 24-bit counter. After s/w reset, MPC

is cleared. Only the lower 3 bytes are valid.

When written any value, MPC will be reset also.

93C46 Command Register

Configuration Register 0

Configuration Register 1

1999/5/30

9

Ver.1.1

Share Link: