PM4318-BI データシートの表示（PDF） - PMC-Sierra

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PM4318-BI

OCTAL E1/T1/J1 LINE INTERFACE DEVICE

PMC-Sierra 

PRELIMINARY

DATASHEET

PMC- 2001578

ISSUE 3

PM4318 OCTLIU

OCTAL E1/T1/J1 LINE INTERFACE DEVICE

FIGURE 25 – LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS ..................... 209

FIGURE 26 – SBI BUS FUNCTIONAL TIMING ...................................................................... 210

FIGURE 27 – B8ZS LINE CODE VIOLATION INSERTION ................................................... 211

FIGURE 28 – HDB3 LINE CODE VIOLATION INSERTION................................................... 212

FIGURE 29 – AMI LINE CODE VIOLATION INSERTION ...................................................... 213

FIGURE 30 – LOS ALARM SERIAL OUTPUT........................................................................ 213

FIGURE 31 – MICROPROCESSOR INTERFACE READ TIMING......................................... 218

FIGURE 32 – MICROPROCESSOR INTERFACE WRITE TIMING ....................................... 220

FIGURE 33 – RSTB TIMING................................................................................................... 221

FIGURE 34 – XCLK INPUT TIMING ....................................................................................... 221

FIGURE 35 – TRANSMIT SERIAL INTERFACE TIMING DIAGRAM..................................... 222

FIGURE 36 – RECEIVE SERIAL INTERFACE TIMING DIAGRAM ....................................... 223

FIGURE 37 – SBI FRAME PULSE TIMING............................................................................ 224

FIGURE 38 – SBI ADD BUS TIMING ..................................................................................... 225

FIGURE 39 – SBI DROP BUS TIMING .................................................................................. 226

FIGURE 40 – SPI INTERFACE TIMING ................................................................................. 227

FIGURE 41 – ALARM INTERFACE TIMING........................................................................... 228

FIGURE 42 – INGRESS CLK/DATA INTERFACE TIMING DIAGRAM................................... 229

FIGURE 43 – EGRESS CLK/DATA INTERFACE TIMING DIAGRAM.................................... 229

FIGURE 44 – JTAG PORT INTERFACE TIMING ................................................................... 231

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

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