PM4318-BI データシートの表示（PDF） - PMC-Sierra

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PM4318-BI

OCTAL E1/T1/J1 LINE INTERFACE DEVICE

PMC-Sierra 

PRELIMINARY

DATASHEET

PMC- 2001578

ISSUE 3

PM4318 OCTLIU

OCTAL E1/T1/J1 LINE INTERFACE DEVICE

LIST OF FIGURES

FIGURE 1 – T1/E1 FRAMER/TRANSCEIVER APPLICATION................................................. 7

FIGURE 2 – HIGH DENSITY T1/E1 FRAMER/TRANSCEIVER APPLICATION ...................... 7

FIGURE 3 – HIGH DENSITY LEASED LINE CIRCUIT EMULATION APPLICATION.............. 7

FIGURE 4 – METRO OPTICAL ACCESS EQUIPMENT .......................................................... 8

FIGURE 5 – OCTLIU BLOCK DIAGRAM – LIUS ENABLED ................................................... 9

FIGURE 6 – OCTLIU BLOCK DIAGRAM – SBI TO CLK/DATA CONVERTER, LIUS

DISABLED .......................................................................................................... 10

FIGURE 7 – PIN DIAGRAM.................................................................................................... 12

FIGURE 8 – EXTERNAL ANALOGUE INTERFACE CIRCUITS ............................................ 35

FIGURE 9 – T1 JITTER TOLERANCE ................................................................................... 37

FIGURE 10 – COMPLIANCE WITH ITU-T SPECIFICATION G.823 FOR E1 INPUT JITTER . 38

FIGURE 11 – TJAT JITTER TOLERANCE ............................................................................... 41

FIGURE 12 – TJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY........................ 42

FIGURE 13 – TJAT JITTER TRANSFER.................................................................................. 43

FIGURE 14 – SBI TO FRAMER LINE SIDE INTERFACE ........................................................ 45

FIGURE 15 – SERIAL PROM CASCADE INTERFACE ........................................................... 46

FIGURE 16 – SERIAL PROM COMMAND FORMAT ............................................................... 47

FIGURE 17 – TRANSMIT TIMING OPTIONS........................................................................... 75

FIGURE 18 – LINE LOOPBACK............................................................................................. 202

FIGURE 19 – DIAGNOSTIC DIGITAL LOOPBACK................................................................ 202

FIGURE 20 – BOUNDARY SCAN ARCHITECTURE ............................................................. 203

FIGURE 21 – TAP CONTROLLER FINITE STATE MACHINE ............................................... 205

FIGURE 22 – INPUT OBSERVATION CELL (IN_CELL) ........................................................ 208

FIGURE 23 – OUTPUT CELL (OUT_CELL) OR ENABLE CELL (ENABLE).......................... 208

FIGURE 24 – BIDIRECTIONAL CELL (IO_CELL) .................................................................. 209

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

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