PDI1394L21 データシートの表示（PDF） - Philips Electronics
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PDI1394L21 Datasheet PDF : 52 Pages
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Philips Semiconductors
1394 full duplex AV link layer controller
Preliminary specification
PDI1394L21
14.1 Pin Categories
Table 11. Pin Categories
Category 1:
Input/Output
Category 2:
Input
Category 3:
Input
Category 4:
Output
HIF D[7:0] HIF A[8:0]
RESET_N CYCLEOUT
AVxSYNC HIF CS_N
CYCLEIN AVxERR0
AVxVALID HIF WR_N
ISO_N
AVxERR1
AV xD[7:0] HIF RD_N
CLK25
AVxENKEY AVxENDPCK
AVxCLK
AVxFSYNC
Category 5:
Output
HIF INT_N
Category 6:
Input/Output
PHY D[0:7]
PHY CTL[0:1]
Category 7: Category 8:
LREQ
SCLK
15.0 AC CHARACTERISTICS
GND = 0V, CL = 50pF
SYMBOL
PARAMETER
TEST CONDITIONS
tPERIOD
tSU
tIH
tOD
tWHIGH
tWLOW
tPWFS
tSUP
tHP
tSCLKPER
tDP
tAS
tAH
tCL
tCH
tRP
tACC
tDH
tDS
tDZ
tWRP
tCWH
tCWL
tCP
tCD
tRESET
AV clock period
AV clock setup time
AV clock input hold time
AV clock output delay time
AV clock pulse width HIGH
AV clock pulse width LOW
AVxFSYNC pulse width HIGH
PHY-link setup time
PHY-link hold time
SCLK period
PHY-link output delay
Host address setup time
Host address hold time
Host chip select pulse width LOW
Host chip select pulse width HIGH
Host read pulse width
Host access time
Host data hold time
Host data setup time
Host data bus release (Hi-Z)
Host write pulse width
CYCLEIN HIGH pulse width
CYCLEIN LOW pulse width
CYCLEIN cycle period
CYCLEOUT cycle delay
RESET_N pulse width LOW
Note: CL = 20pF
WAVEFORMS
Figure 26
Figure 26
Figure 26
Figure 26
Figure 26
Figure 26
Figure 27
Figure 28
Figure 28
Figure 28
Figure 29
Figure 30
Figure 30
Figure 30
Figure 30
Figure 30
Figure 30
Figure 30
Figure 30
Figure 30
Figure 30
Figure 31
Figure 31
Figure 31
Figure 32
Figure 33
LIMITS
Tamb = 0°C to +70°C
MIN
TYP MAX
41.67
20
3
3
24
10
10
100
140
6.0
0
20.343 20.345 20.347
2.0
10.0
0
0
115
42
115
115
0
0
15
115
200
200
125
20
10
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
1999 Aug 06
45
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