PCK2002DGG データシートの表示（PDF） - Philips Electronics

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PCK2002DGG

0–300 MHz I2C 1:18 clock buffer

Philips Electronics 

Philips Semiconductors

0–300 MHz I2C 1:18 clock buffer

Product data

PCK2002

Byte 2: SDRAM Output active/inactive register

1 = enable; 0 = disable

BIT(S)

AFFECTED PIN

PIN NO.

PIN NAME

CONTROL FUNCTION

7

N/A

BUF_OUT17

Clock Output Disable

6

12

BUF_OUT16

Clock Output Disable

5

N/A

Reserved

(Reserved)

4

N/A

Reserved

(Reserved)

3

N/A

Reserved

(Reserved)

2

N/A

Reserved

(Reserved)

1

N/A

Reserved

(Reserved)

0

N/A

Reserved

(Reserved)

NOTE:

1. At power up all SDRAM outputs are enabled and active. Program all reserved bits to “0”.

BIT CONTROL

0

1

Low

Active

Low

Active

—

—

—

—

—

—

—

—

—

—

—

—

2001 Jul 19

8

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