PCK2002DGG データシートの表示（PDF） - Philips Electronics

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PCK2002DGG

0–300 MHz I2C 1:18 clock buffer

Philips Electronics 

Philips Semiconductors

0–300 MHz I2C 1:18 clock buffer

Product data

PCK2002

DC CHARACTERISTICS

SYMBOL

VIH

VIL

VOH

VOL

IOH

IOL

±II

±IOZ

ICC

∆ICC

PARAMETER

HIGH level input voltage

LOW level input voltage

3.3V output HIGH voltage

3.3V output LOW voltage

Output HIGH current

Output LOW current

Input leakage current

3-State output OFF-State current

Quiescent supply current

Additional quiescent supply

current given per control pin

TEST CONDITIONS

VDD (V)

3.135 to 3.465

3.135 to 3.465

3.135 to 3.465

3.135

3.135 to 3.465

3.135

3.135

3.465

3.135 to 3.465

3.135 to 3.465

3.465

3.465

3.465

3.135 to 3.465

OTHER

IOH = –1 mA

IOH = –36 mA

IOL= 1 mA

IOL= 24 mA

VOUT = 2.0 V

VOUT = 3.135 V

VOUT = 1.0 V

VOUT = 0.4 V

VOUT = VDDor GND

VI = VDD or GND

VI = VDD– 0.6V

IO = 0

IO = 0

IO = 0

LIMITS

Tamb = 0 to +70 °C

MIN

MAX

2.0

VSS – 0.3

VCC – 0.1

2.4

VDD + 0.3

0.8

—

—

—

0.1

—

0.4

–54

–126

–21

–46

49

118

24

53

—

±5

—

10

—

100

—

500

UNIT

V

V

V

V

mA

mA

µA

µA

µA

µA

AC CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

NOTES

LIMITS

Tamb = 0 to +70 °C

MIN

TYP6

MAX

UNIT

TSDRISE

SDRAM rise time

2, 4

1.5

2.0

4.0

V/ns

TSDFALL

SDRAM fall time

2, 4

1.5

2.9

4.0

V/ns

TPLH

SDRAM buffer LH propagation delay

4, 5

1.2

2.7

3.5

ns

TPHL

SDRAM buffer HL propagation delay

4, 5

1.2

2.9

3.5

ns

TPZL, TPZH

SDRAM buffer enable time

4, 5

1.0

2.6

5.0

ns

TPLZ, TPHZ

SDRAM buffer disable time

4, 5

1.0

2.7

5.0

ns

DUTY CYCLE

Output Duty Cycle

Measured at 1.5 V 3, 4, 5

45

52

55

%

TSDSKW

SDRAM Bus CLK skew

1, 4

—

150

250

ps

TDDSKW

Device to device skew

—

—

500

ps

NOTES:

1. Skew is measured on the rising edge at 1.5 V.

2. TSDRISE and TSDFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1mA) JEDEC specification.

3. Duty cycle should be tested with a 50/50% input.

4. Over MIN (20 pF) to MAX (30 pF) discrete load, process, voltage, and temperature.

5. Input edge rate for these tests must be faster than 1 V/ns.

6. All typical values are at VCC = 3.3 V and Tamb = 25 °C.

2001 Jul 19

4

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