PCF2105 データシートの表示（PDF） - Philips Electronics

部品番号

コンポーネント説明

一致するリスト

PCF2105

LCD controller/driver

Philips Electronics 

Philips Semiconductors

LCD controller/driver

Product specification

PCF2105

9.6 Function set

9.6.1 DL (PARALLEL MODE ONLY)

Bit DL sets the interface data length. Data is sent or

received in bytes (DB7 to DB0) when DL = 1 or in two

nibbles (DB7 to DB4) when DL = 0. When 4-bit length is

selected, data is transmitted in two cycles using the

parallel bus. In a 4-bit application DB3 to DB0 are left open

(internal pull-ups).

DL can not be set to logic 0 from the I2C-bus interface.

If DL has been set to logic 0 via the parallel bus,

programming via the I2C-bus interface is complicated.

9.6.2 N AND M

Bits N and M set the number of display lines.

9.7 Set CGRAM address

‘Set CGRAM address’ sets bits 0 to 5 of the CGRAM

address (ACG in Table 3) into the AC (binary A[5] to A[0]).

Data can then be written to or read from the CGRAM.

Only bits 0 to 5 of the CGRAM address are set by the ‘set

CGRAM address’ instruction. Bit 6 can be set using the

‘set DDRAM address’ instruction or by using the

auto-increment feature during CGRAM write. All bits 0 to 6

can be read using the ‘read busy flag and address’

instruction.

9.8 Set DDRAM address

‘Set DDRAM address’ sets the DDRAM address (ADD in

Table 3) into the AC (binary A[6] to A[0]). Data can then be

written to or read from the DDRAM.

Table 5 Hexadecimal address ranges

ADDRESS

FUNCTION

00 to 4F

1 line of 24 characters

00 to 0B and 0C to 4F

2 lines of 12 characters

00 to 27 and 40 to 67

2 lines of 24 characters

00 to 13, 20 to 33, 40 to 53 4 lines of 12 characters

and 60 to 73

9.9 Read busy flag and address

‘Read busy flag and address’ reads the Busy Fag (BF).

When bit BF = 1 it indicates that an internal operation is in

progress. The next instruction will not be executed until

BF = 0, so BF should be checked before sending another

instruction.

At the same time, the value of the AC expressed in binary

A[6] to A[0] is read out. The address counter is used by

both CGRAM and DDRAM and its value is determined by

the previous instruction.

9.10 Write data to CGRAM or DDRAM

‘Write data’ writes binary 8-bit data (D[7] to D[0]) to the

CGRAM or the DDRAM.

Whether the CGRAM or DDRAM is to be written to is

determined by the previous specification of CGRAM or

DDRAM address setting. After writing, the address

automatically increments or decrements by 1, in

accordance with the ‘entry mode set‘.

Only bits D[4] to D[0] of CGRAM data are valid,

bits D[7] to D[5] are ‘don’t care’.

9.11 Read data from CGRAM or DDRAM

‘Read data’ reads binary 8-bit data D[7] to D[0] from the

CGRAM or DDRAM.

The most recent ‘set address’ instruction determines

whether the CGRAM or DDRAM is to be read.

The ‘read data’ instruction gates the content of the

Data Register (DR) to the bus while pad E = HIGH. After E

goes LOW again, internal operation increments

(or decrements) the AC and stores RAM data

corresponding to the new AC into the DR.

Remark: the only three instructions that update the DR are:

• ‘Set CGRAM address’

• ‘Set DDRAM address’

• ‘Read data’ from CGRAM or DDRAM.

Other instructions (e.g. ‘write data’, ‘cursor/display shift’,

‘clear display’, ‘return home’) will not change the data

register content.

1998 Jul 30

19

Share Link: