SL74HC323 データシートの表示（PDF） - System Logic Semiconductor

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SL74HC323

8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Performance Silicon-Gate CMOS

System Logic Semiconductor 

SL74HC323

FUNCTION TABLE

Inputs

Response

Mode

Reset

Reset

L

Mode

Select

S2 S1

XL

Output

Enables

OE1 OE2

LL

Clock

Serial PA/ PB/ PC/ PD/ PE/ PF/ PG/ PH/ QA’ QH’

Inputs QA QB QC QD QE QF QG QH

DA DH

X X LLLL L LL L L L

L LX L L

X X LLLL L LL L L L

L HH X X

Shift H L H H X

Right

H LH X H

H LH L L

Shift H H L H X

Left

H HL X H

H HL L L

Parallel H H H X X

Load

X XX

DX

DX

DX

XD

XD

XD

XX

QA through QH=Z

Shift Right: QA through QH=Z;

DA FA; FA FB; etc

Shift Right: QA through QH=Z;

DA FA; FA FB; etc

Shift Right: DA FA =QA;

FA FB =QB; etc

Shift Left: QA through QH=Z;

DH FH; FH FG; etc

Shift Left: QA through QH=Z;

DH FH; FH FG; etc

Shift Left: DH FH =QH;

FH FG =QG; etc

Parallel Load:PN FN

LL

D QG

D QG

D QG

QB D

QB D

QB D

PA PH

Hold

H LL H X

X X X Hold: QA through QH=Z; FN=FN PA PH

H LL X H

X X X Hold: QA through QH=Z; FN=FN PA PH

H L L L L X XX

Hold: QN =QH

PA PH

Z = high impedance

D = data on serial input

F = flip-flop (see Logic Diagram)

When one or both output controls are high the eight input/output terminals are disabled to the high-impedance

state; however, sequential operation or clearing of the register is not affected.

SLS

System Logic

Semiconductor

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