SL74HC323 データシートの表示（PDF） - System Logic Semiconductor
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SL74HC323
System Logic Semiconductor
SL74HC323 Datasheet PDF : 7 Pages
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SL74HC323
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
VCC
Guaranteed Limit
V 25 °C to-55°C ≤85°C ≤125°C Unit
tsu
Minimum Setup Time, Mode Select S1 2.0
100
or S2 to Clock (Figure 4)
4.5
20
6.0
17
125
150
ns
25
30
21
26
tsu
Minimum Setup Time, Data Inputs SA, 2.0
100
SH, PA thru PH to Clock
4.5
20
(Figure 4)
6.0
17
125
150
ns
25
30
21
26
th
Minimum Hold Time, Clock to Mode
2.0
120
Select S1 or S2 (Figure 4)
4.5
24
6.0
20
150
180
ns
30
36
26
31
th
Minimum Hold Time, Clock to Data
2.0
5
Inputs, SA, SH, PA thru PH (Figure 4)
4.5
5
6.0
5
5
5
ns
5
5
5
5
tw
Minimum Pulse Width, Clock (Figure 2.0
80
1)
4.5
16
6.0
14
100
120
ns
20
24
17
20
tw
Minimum Pulse Width, Reset (Figure 2.0
80
2)
4.5
16
6.0
14
100
120
ns
20
24
17
20
tr, tf Maximum Input Rise and Fall Times
2.0
1000
(Figure 1)
4.5
500
6.0
400
1000
1000
ns
500
500
400
400
SLS
System Logic
Semiconductor
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