MC9S08SF4 データシートの表示（PDF） - Freescale Semiconductor

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MC9S08SF4

8-Bit S08 Central Processor Unit (CPU)

Freescale Semiconductor 

ESD Protection and Latch-Up Immunity

TA = Ambient temperature, °C

θJA = Package thermal resistance, junction-to-ambient, °C/W

PD = Pint + PI/O

Pint = IDD × VDD, Watts — chip internal power

PI/O = Power dissipation on input and output pins — user determined

For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ

(if PI/O is neglected) is:

PD = K ÷ (TJ + 273°C)

Eqn. 2

Solving Equation 1 and Equation 2 for K gives:

K = PD × (TA + 273°C) + θJA × (PD)2

Eqn. 3

where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring

PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by

solving Equation 1 and Equation 2 iteratively for any value of TA.

3.5 ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early

CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.

Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels

of static without suffering any permanent damage.

During the device qualification ESD stresses were performed for the human body model (HBM) and the

charge device model (CDM).

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification. Complete DC parametric and functional testing is performed per the applicable device

specification at room temperature followed by hot temperature, unless specified otherwise in the device

specification.

MC9S08SF4 Series MCU Data Sheet, Rev. 2

Freescale Semiconductor

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