NLV74HC74ADTR2G(2014) データシートの表示（PDF） - ON Semiconductor
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NLV74HC74ADTR2G Datasheet PDF : 7 Pages
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MC74HC74A
Dual D Flip-Flop with Set
and Reset
High−Performance Silicon−Gate CMOS
The MC74HC74A is identical in pinout to the LS74. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two D flip−flops with individual Set, Reset,
and Clock inputs. Information at a D−input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip−flop. The Set
and Reset inputs are asynchronous.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 128 FETs or 32 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
LOGIC DIAGRAM
RESET 1 1
DATA 1 2
3
CLOCK 1
5
Q1
6
Q1
SET 1 4
13
RESET 2
DATA 2 12
11
CLOCK 2
10
SET 2
9
Q2
8
Q2
PIN 14 = VCC
PIN 7 = GND
http://onsemi.com
SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
RESET 1 1
DATA 1 2
CLOCK 1 3
SET 1 4
Q1 5
Q1 6
GND 7
14 VCC
13 RESET 2
12 DATA 2
11 CLOCK 2
10 SET 2
9 Q2
8 Q2
MARKING DIAGRAMS
14
HC74AG
AWLYWW
1
SOIC−14 NB
14
HC
74A
ALYWG
G
1
TSSOP−14
A
L, WL
Y, YY
W, WW
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 14
Publication Order Number:
MC74HC74A/D
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