M80C287 データシートの表示（PDF） - Intel

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M80C287

80-BIT CHMOS III NUMERIC PROCESSOR EXTENSION

Intel 

M80C287

ERROR STATUS (ERROR)

This pin reflects the ES bit of the status register

When active it indicates that an unmasked excep-

tion has occurred This signal can be changed to

inactive state only by the following instructions (with-

out a preceding WAIT) FNINIT FNCLEX

FNSTENV FNSAVE FLDCW FLDENV and

FRSTOR This pin should be connected to the

ERROR pin of the CPU ERROR can change state

only when BUSY is active

PROCESSOR EXTENSION ACKNOWLEDGE

(PEACK)

During execution of escape instructions an M80286

or M80C286 CPU asserts PEACK to acknowledge

that the request signal (PEREQ) has been recog-

nized and that data transfer is in progress The

M80286 M80C286 also drives this signal HIGH dur-

ing RESET

This input may be asynchronous with respect to the

M80C287 clock except during a RESET sequence

when it must satisfy setup and hold requirements

relative to RESET

DATA PINS (D15 – D0)

These bidirectional pins are used to transfer data

and opcodes between the CPU and M80C287 They

are normally connected directly to the correspond-

ing CPU data pins Other buffers drivers driving the

local data bus must be disabled when the CPU

reads from the NPX HIGH state indicates a value of

one D0 is the least significant data bit

NUMERIC PROCESSOR WRITE (NPWR)

A signal on this pin enables transfers of data from

the CPU to the NPX This input is valid only when

NPS1 and NPS2 are both active

NUMERIC PROCESSOR READ (NPRD)

A signal on this pin enables transfers of data from

the NPX to the CPU This input is valid only when

NPS1 and NPS2 are both active

NUMERIC PROCESSOR SELECTS (NPS1 and

NPS2)

Concurrent assertion of these signals indicates that

the CPU is performing an escape instruction and en-

ables the M80C287 to execute that instruction No

data transfer involving the M80C287 occurs unless

the device is selected by these lines

COMMAND SELECTS (CMD0 AND CMD1)

These pins along with the select pins allow the CPU

to direct the operation of the M80C287

SYSTEM POWER (VCC)

System power provides the a5Vg5% DC supply

input All VCC pins should be tied together on the

circuit board and local decoupling capacitors should

be used between VCC and VSS

SYSTEM GROUND (VSS)

All VSS pins should be tied together on the circuit

board and local decoupling capacitors should be

used between VCC and VSS

Processor Architecture

As shown by the block diagram on the front page

the M80C287 NPX is internally divided into three

sections the bus control logic (BCL) the data inter-

face and control unit and the floating point unit

(FPU) The FPU (with the support of the control unit

which contains the sequencer and other support

units) executes all numerics instructions The data

interface and control unit is responsible for the data

flow to and from the FPU and the control registers

for receiving the instructions decoding them and

sequencing the microinstructions and for handling

some of the administrative instructions The BCL is

responsible for CPU bus tracking and interface

BUS CONTROL LOGIC

The BCL communicates solely with the CPU using I

O bus cycles The BCL appears to the CPU as a

special peripheral device It is special in two re-

spects the CPU initiates I O automatically when it

encounters ESC instructions and the CPU uses re-

served I O addresses to communicate with the BCL

The BCL does not communicate directly with memo-

ry The CPU performs all memory access transfer-

ring input operands from memory to the M80C287

and transferring outputs from the M80C287 to mem-

ory A dedicated communication protocol makes

possible high-speed transfer of opcodes and oper-

ands between the M80C286 CPU and M80C287

DATA INTERFACE AND CONTROL UNIT

The data interface and control unit latches the data

and subject to BCL control directs the data to the

FIFO or the instruction decoder The instruction de-

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