TEST CIRCUIT
Qn
CL=30pF : tAC, tOH
MITSUBISHI 〈DIGITAL ASSP〉
M66256FP
5120 × 8-BIT LINE MEMORY (FIFO)
VCC
RL=1kΩ
SW1
Qn
SW2
RL=1kΩ
CL=5pF : tOEN, tODIS
Input pulse level
: 0 ~ 3V
Input pulse rise/fall time : 3ns
Decision voltage input : 1.3V
Decision voltage output : 1.3V (However, tODIS(LZ) is 10% of output amplitude and tODIS(HZ) is 90% of
that for decision).
The load capacitance CL includes the floating capacitance of connection and the input capacitance of
probe.
Parameter
tODIS(LZ)
tODIS(HZ)
tOEN(ZL)
tOEN(ZH)
SW1
Closed
Open
Closed
Open
SW2
Open
Closed
Open
Closed
tODIS/tOEN TEST CONDITION
RCK
1.3V
RE
tODIS(HZ)
Qn
90%
tODIS(LZ)
Qn
10%
1.3V
tOEN(ZH)
1.3V
tOEN(ZL)
1.3V
3V
GND
3V
GND
VOH
VOL
4