DS_K9F1208U0M データシートの表示（PDF） - Samsung
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DS_K9F1208U0M Datasheet PDF : 41 Pages
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K9F1208U0M-YCB0, K9F1208U0M-YIB0
FLASH MEMORY
Figure 1. Functional Block Diagram
VCC
VSS
A9 - A25
A0 - A7
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
512M + 16M Bit
NAND Flash
ARRAY
(512 + 16)Byte x 131072
Command
A8
Command
Register
CE
Control Logic
RE
& High Voltage
WE
Generator
Page Register & S/A
Y-Gating
I/O Buffers & Latches
VCC
VSS
Global Buffers
Output
I/0 0
Driver
I/0 7
CLE ALE WP
Figure 2. Array Organization
1 Block = 32 Pages
(16K + 512) Byte
128K Pages
(=4,096 Blocks)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
512B Bytes
16 Bytes
1 Page = 528 Bytes
1 Block = 528 B x 32 Pages
= (16K + 512) Bytes
1 Device = 528B x 32Pages x 4,096 Blocks
= 528 Mbits
8 bit
Page Register
512 Bytes
I/O 0 ~ I/O 7
16 Bytes
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
1st Cycle
A0
A1
A2
A3
A4
A5
A6
2nd Cycle A9
A10
A11
A12
A13
A14
A15
3rd Cycle A17
A18
A19
A20
A21
A22
A23
4th Cycle A25
*L
*L
*L
*L
*L
*L
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
I/O 7
A7
A16
A24
*L
Column Address
Row Address
(Page Address)
7
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