ISP1562BE データシートの表示（PDF） - Philips Electronics
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ISP1562BE Datasheet PDF : 98 Pages
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Philips Semiconductors
ISP1562
USB PCI Host Controller
Table 13: CLS - CacheLine Size register (address 0Ch) bit description
Legend: * reset value
Bit Symbol Access Value Description
7 to 0 CLS[7:0] R/W
00h*
CacheLine Size: This byte identifies the system
CacheLine size.
8.2.1.8 Latency Timer register
This register specifies—in units of PCI bus clocks—the value of the Latency Timer for the
PCI bus master. Table 14 shows the bit description of the Latency Timer register.
Table 14: LT - Latency Timer register (address 0Dh) bit description
Legend: * reset value
Bit
Symbol Access Value Description
7 to 0 LT[7:0] R/W
00h* Latency Timer: This byte identifies the latency timer.
8.2.1.9 Header Type register
The Header Type register identifies the layout of the second part of the predefined header,
beginning at byte 10h in configuration space. It also identifies whether the device contains
multiple functions. For bit allocation, see Table 15.
Table 15: Header Type register (address 0Eh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
MFD
HT[6:0]
Reset
1
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Table 16: Header Type register (address 0Eh) bit description
Bit
Symbol
Description
7
MFD
Multi-Function Device: This bit identifies a multifunction device.
0 — The device has single function.
1 — The device has multiple functions.
6 to 0
HT[6:0]
Header Type: These bits identify the layout of the part of the
predefined header, beginning at byte 10h in configuration space.
8.2.1.10 Base Address register 0
Power-up software must build a consistent address map before booting the machine to an
operating system. This means it must determine how much memory is in the system, and
how much address space the I/O controllers in the system require. After determining this
information, power-up software can map the I/O controllers into reasonable locations and
proceed with system boot. To do this mapping in a device-independent manner, the base
registers for this mapping are placed in the predefined header portion of configuration
space.
Bit 0 in all Base Address registers is read-only and used to determine whether the register
maps into memory or I/O space. Base Address registers that map to memory space must
return logic 0 in bit 0. Base Address registers that map to I/O space must return logic 1 in
bit 0.
The bit description of the BAR 0 register is given in Table 17.
9397 750 14223
Product data sheet
Rev. 01 — 14 July 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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