ISP1562BE データシートの表示（PDF） - Philips Electronics

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ISP1562BE

Hi-Speed Universal Serial Bus PCI Host Controller

Philips Electronics 

Philips Semiconductors

ISP1562

USB PCI Host Controller

7.7 Power-On Reset (POR)

Figure 3 shows a possible curve of VCC(I/O) with dips at t2 to t3 and t4 to t5. At t0, POR will

start with 1. At t1, the detector passes through the trip level. Another delay will be added

before POR drops to 0 to ensure that the length of the generated detector pulse, POR, is

large enough to reset asynchronous flip-flops. If the dip is too short (t4 to t5 < 11 µs),

POR will not react and will stay LOW.

t0

t1

t2

t3

VPOR(trip) is typically 1.2 V.

Fig 3. Power-on reset.

VCC(I/O)

VPOR(trip)

t4 t5

POR

004aaa664

7.8 Power supply

Figure 4 shows the ISP1562 power supply connection.

9397 750 14223

Product data sheet

Rev. 01 — 14 July 2005

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

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