ISL8500 データシートの表示（PDF） - Intersil

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ISL8500

2A Standard Buck PWM Regulator

Intersil 

ISL8500

Typical Performance Curves

Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 12V, EN = VDD, L = 10µH,

COUT = 100µF, C2 = 2x22µF, IOUT = 0A to 2A. See “The input supply for the PWM regulator

power stage and the source for the internal linear regulator that provides bias for the IC. Place a

ceramic capacitor from VIN to GND, close to the IC for decoupling (typical 10µF).” on page 6.

100

90

2.5VOUT 1.8VOUT

80

70

60

1.2VOUT 1.5VOUT

50

40

3.3VOUT

30

20

0.0

0.5

1.0

1.5

2.0

OUTPUT LOAD (A)

FIGURE 2. EFFICIENCY vs LOAD, 5VIN

100

2.5VOUT 3.3VOUT

5VOUT

90

80

70

1.8VOUT

60

1.5VOUT

50

1.2VOUT

40

30

20

0.0

0.5

1.0

1.5

2.0

OUTPUT LOAD (A)

FIGURE 3. EFFICIENCY vs LOAD, 12VIN

100

12VOUT

90

80

5VOUT

70

60

1.5VOUT 2.5VOUT

50

1.2VOUT

40

1.8VOUT

30

20

0.0

0.5

1.0

1.5

2.0

OUTPUT LOAD (A)

FIGURE 4. EFFICIENCY vs LOAD, 25VIN

1.6

1.4

1.2

1.0

0.8

25VIN

0.6

12VIN

0.4

0.2

5VIN

0.0

0.0

0.5

1.0

1.5

2.0

OUTPUT LOAD (A)

FIGURE 5. POWER DISSIPATION vs LOAD, 2.5VOUT

1.206

1.205

1.204

12VIN

25VIN

1.203

1.202

1.201

1.200

5VIN

1.199

1.198

0.0

0.5

1.0

1.5

2.0

OUTPUT LOAD (A)

FIGURE 6. VOUT REGULATION vs LOAD, 1.2VOUT

1.510

1.509

1.508

12VIN

25VIN

1.507

1.506

1.505

1.504

5VIN

1.503

1.502

0.0

0.5

1.0

1.5

2.0

OUTPUT LOAD (A)

FIGURE 7. VOUT REGULATION vs LOAD, 1.5VOUT

7

FN6611.0

December 10, 2007

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