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IDT82P20416 データシートの表示(PDF) - Integrated Device Technology

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IDT82P20416
IDT
Integrated Device Technology IDT
IDT82P20416 Datasheet PDF : 121 Pages
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IDT82P20416
16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
3.5.1.1 Bipolar Violation (BPV) / Code Violation (CV) Detection ............................................................. 33
3.5.1.2 Bipolar Violation (BPV) Insertion ................................................................................................. 33
3.5.2 Excessive Zeroes (EXZ) Detection ............................................................................................................. 33
3.5.3 Loss of Signal (LOS) Detection ................................................................................................................... 34
3.5.3.1 Line LOS (LLOS) ......................................................................................................................... 34
3.5.3.2 System LOS (SLOS) ................................................................................................................... 35
3.5.3.3 Transmit LOS (TLOS) ................................................................................................................. 36
3.5.4 Alarm Indication Signal (AIS) Detection and Generation ............................................................................ 37
3.5.4.1 Alarm Indication Signal (AIS) Detection ...................................................................................... 37
3.5.4.2 (Alarm Indication Signal) AIS Generation ................................................................................... 37
3.5.5 PRBS, QRSS, ARB and IB Pattern Generation and Detection ................................................................... 38
3.5.5.1 Pattern Generation ...................................................................................................................... 38
3.5.5.2 Pattern Detection ........................................................................................................................ 39
3.5.6 Error Counter .............................................................................................................................................. 40
3.5.6.1 Automatic Error Counter Updating .............................................................................................. 40
3.5.6.2 Manual Error Counter Updating .................................................................................................. 41
3.5.7 Loopback .................................................................................................................................................... 42
3.5.7.1 Analog Loopback ........................................................................................................................ 42
3.5.7.2 Remote Loopback ....................................................................................................................... 43
3.5.7.3 Digital Loopback .......................................................................................................................... 44
3.5.8 Channel 0 Monitoring .................................................................................................................................. 45
3.5.8.1 G.772 Monitoring ......................................................................................................................... 45
3.5.8.2 Jitter Measurement (JM) ............................................................................................................. 46
3.6 CLOCK INPUTS AND OUTPUTS ............................................................................................................................ 47
3.6.1 Free Running Clock Outputs on CLKT1/CLKE1 ......................................................................................... 47
3.6.2 MCLK, Master Clock Input .......................................................................................................................... 48
3.6.3 XCLK, Internal Reference Clock Input ........................................................................................................ 48
3.7 INTERRUPT SUMMARY ......................................................................................................................................... 49
4 MISCELLANEOUS .......................................................................................................................................................... 51
4.1 RESET ..................................................................................................................................................................... 51
4.1.1 Power-On Reset ......................................................................................................................................... 52
4.1.2 Hardware Reset .......................................................................................................................................... 52
4.1.3 Global Software Reset ................................................................................................................................ 52
4.1.4 Per-Channel Software Reset ...................................................................................................................... 52
4.2 MICROPROCESSOR INTERFACE ......................................................................................................................... 52
4.3 POWER UP .............................................................................................................................................................. 53
4.4 HITLESS PROTECTION SWITCHING (HPS) SUMMARY ...................................................................................... 53
5 PROGRAMMING INFORMATION ................................................................................................................................... 56
5.1 REGISTER MAP ...................................................................................................................................................... 56
5.1.1 Global Register ........................................................................................................................................... 56
5.1.2 Per-Channel Register ................................................................................................................................. 57
5.2 REGISTER DESCRIPTION ..................................................................................................................................... 60
5.2.1 Global Register ........................................................................................................................................... 60
5.2.2 Per-Channel Register ................................................................................................................................. 65
Table of Contents
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December 17, 2009

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