IDTCV125 データシートの表示（PDF） - Integrated Device Technology

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IDTCV125

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

Integrated Device Technology 

IDTCV125

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

BYTE 9

Bit

0

1

2

3

4

5

6

7

Output(s) Affected

One cycle read

SRC, PLL2, SSC enable

Description / Function

N Programming enable

LVDS PLL power down

USB PLL power down

SRC PLL power down

CPU PLL power down

Only valid when Byte1 bit0 is 1

BYTE 10

Bit

0

1

2

3

4

5

6

7

Output(s) Affected

SRC SMC0

SRC SMC1

SRC SMC2

Reserved

CPU SMC0

CPU SMC1

CPU SMC2

Reserved

Description / Function

SRC/PCI SSC control

see SMC table

CPU PLL SSC control

see SMC table

0

disable

Disable

normal

normal

normal

normal

disable

0

BYTE 11

Bit

Output(s) Affected

Description / Function

0

0

CPU_N0, LSB

CPU CLK = N* Resolution

1

CPU_N1

see Resolution table

2

CPU_N2

3

CPU_N3

4

CPU_N4

5

CPU_N5

6

CPU_N6

7

CPU_N7, MSB

COMMERCIAL TEMPERATURE RANGE

1

enable

enable

Power down

Power down

Power down

Power down

enable

Type

Power On

RW

0

RW

0

RW

0

RW

0

RW

0

RW

0

RW

0

RW

1

1

Type

Power On

RW

1

RW

0

RW

0

RW

0

RW

1

RW

0

RW

0

RW

0

1

Type

Power On

RW

0

RW

1

RW

1

RW

0

RW

1

RW

0

RW

0

RW

1

BYTE 12

Bit

Output(s) Affected

Description / Function

0

1

Type

Power On

0

SRC_N0, LSB

RW

0

1

SRC_N1

RW

1

2

SRC_N2

SRC f = N*SRC Resolution

RW

1

3

SRC_N3

Resolution = 0.666667

RW

0

4

SRC_N4

100MHz N= 150

RW

1

5

SRC_N5

RW

0

6

SRC_N6

7

SRC_N7, MSB

RW

0

RW

1

9

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