IDTCV125 データシートの表示（PDF） - Integrated Device Technology

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IDTCV125

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

Integrated Device Technology 

IDTCV125

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

COMMERCIAL TEMPERATURE RANGE

CONTROL REGISTERS

N PROGRAMMING PROCEDURE

• Use Index byte write.

• For N programming, the user only needs to access Byte 11, Byte 12, and Byte 9.

1.

Write Byte 11 for CPU PLL N, CPU f = N* Resolution (see resolution table).

2.

Write Byte 12 for SRC PLL N, SRC f = N*0.666667, PCI = SRC f /3.

3.

Enable N Programming bit, Byte 9 bit 1. Once this bit is enabled, any N value will be changed on the fly.

BYTE 0

Bit

0

1

2

3

4

5

6

7

Output(s) Affected

Reserved

SRC1, SRC1#

SRC2, SRC2#

SRC3, SRC3#

SRC4, SRC4#

SRC5, SRC5#

SRC6, SRC6#

CPU2, CPU2#/

SRC7, SRC7#

Description/Function

Output Enable

Output Enable

Output Enable

Output Enable

Output Enable

Output Enable

Output Enable

0

Tristate

Tristate

Tristate

Tristate

Tristate

Tristate

Tristate

1

Enable

Enable

Enable

Enable

Enable

Enable

Enable

Type

Power On

RW

1

RW

1

RW

1

RW

1

RW

1

RW

1

RW

1

BYTE 1

Bit

Output(s) Affected

Description/Function

0

1

Type

Power On

0

CPU[2:0], SRC[7:1],

Spread Spectrum mode enable

Spread off

Spread on

RW

0

PCI[5:0], PCIF[1:0]

1

CPU0, CPU0#

Output Enable

Tristate

Enable

RW

1

2

CPU1, CPU1#

Output Enable

Tristate

Enable

RW

1

3

Reserved

RW

0

4

REF

Output Enable

Tristate

Enable

RW

1

5

USB48

Output Enable

Tristate

Enable

RW

1

6

DOT96

Output Enable

Tristate

Enable

RW

1

7

PCIF0

Output Enable

Tristate

Enable

RW

1

BYTE 2

Bit

0

1

2

3

4

5

6

7

Output(s) Affected

PCIF1

Reserved

PCI0

PCI1

PCI2

PCI3

Reserved

Reserved

Description/Function

Output Enable

Output Enable

Output Enable

Output Enable

Output Enable

0

Tristate

Tristate

Tristate

Tristate

Tristate

1

Enable

Enable

Enable

Enable

Enable

Type

Power On

RW

1

RW

1

RW

1

RW

1

RW

1

RW

1

RW

1

RW

1

6

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