IDT82V2088 データシートの表示（PDF） - Integrated Device Technology

部品番号

コンポーネント説明

一致するリスト

IDT82V2088

OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

LIST OF FIGURES

Figure-1

Figure-2

Figure-3

Figure-4

Figure-5

Figure-6

Figure-7

Figure-8

Figure-9

Figure-10

Figure-11

Figure-12

Figure-13

Figure-14

Figure-15

Figure-16

Figure-17

Figure-18

Figure-19

Figure-20

Figure-21

Figure-22

Figure-23

Figure-24

Figure-25

Figure-26

Figure-27

Figure-28

Figure-29

Figure-30

Figure-31

Figure-32

Figure-33

Figure-34

Figure-35

Figure-36

Figure-37

Block Diagram ................................................................................................................. 2

IDT82V2088 PQFP208 Package Pin Assignment .......................................................... 8

IDT82V2088 PBGA208 Package Pin Assignment (top view) ......................................... 9

E1 Waveform Template Diagram .................................................................................. 16

E1 Pulse Template Test Circuit ..................................................................................... 16

DSX-1 Waveform Template .......................................................................................... 16

T1 Pulse Template Test Circuit ..................................................................................... 17

Receive Path Function Block Diagram .......................................................................... 22

Transmit/Receive Line Circuit ....................................................................................... 22

Monitoring Receive Line in Another Chip ...................................................................... 23

Monitor Transmit Line in Another Chip .......................................................................... 23

G.772 Monitoring Diagram ............................................................................................ 24

Jitter Attenuator ............................................................................................................. 25

LOS Declare and Clear ................................................................................................. 26

Analog Loopback .......................................................................................................... 29

Digital Loopback ............................................................................................................ 29

Remote Loopback ......................................................................................................... 29

Auto Report Mode ......................................................................................................... 31

Manual Report Mode ..................................................................................................... 32

TCLK Operation Flowchart ............................................................................................ 33

Serial Processor Interface Function Timing .................................................................. 34

JTAG Architecture ......................................................................................................... 57

JTAG State Diagram ..................................................................................................... 60

Transmit System Interface Timing ................................................................................ 68

Receive System Interface Timing ................................................................................. 68

E1 Jitter Tolerance Performance .................................................................................. 69

T1/J1 Jitter Tolerance Performance .............................................................................. 69

E1 Jitter Transfer Performance ..................................................................................... 71

T1/J1 Jitter Transfer Performance ................................................................................ 71

JTAG Interface Timing .................................................................................................. 72

Serial Interface Write Timing ......................................................................................... 73

Serial Interface Read Timing with SCLKE=1 ................................................................ 73

Serial Interface Read Timing with SCLKE=0 ................................................................ 73

Non_multiplexed Motorola Read Timing ....................................................................... 74

Non_multiplexed Motorola Write Timing ....................................................................... 75

Non_multiplexed Intel Read Timing .............................................................................. 76

Non_multiplexed Intel Write Timing .............................................................................. 77

7

Share Link: