IDT7133 データシートの表示（PDF） - Integrated Device Technology

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IDT7133

HIGH SPEED 2K X 16 DUAL-PORT SRAM

Integrated Device Technology 

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)

ADDR"A" AND "B"

ADDRESSES MATCH

CE"A"

CE"B"

BUSY"B"

tAPS(2)

tBAC

tBDC

2746 drw 13

Timing Waveform of BUSY Arbitration Controlled by Addresses(1)

ADDR "A"

ADDR "B"

BUSY "B"

tRC OR tWC

ADDRESSES MATCH

tAPS(2)

tBAA

ADDRESSES DO NOT MATCH

tBDA

2746 drw 14

NOTES:

1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted

(IDT7133 only).

61.432

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