IDT7133 データシートの表示（PDF） - Integrated Device Technology

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IDT7133

HIGH SPEED 2K X 16 DUAL-PORT SRAM

Integrated Device Technology 

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1 (R/W Controlled Timing)(1,5,8)

tWC

ADDRESS

OE

CE

R/W(9)

DATAOUT

DATAIN

tAS(6)

tLZ

tAW

tWP(2)

tWZ (7)

(4)

tWR(3)

tOW

tDW

tDH

tHZ(7)

tHZ (7)

(4)

2746 drw 09

Write Cycle No. 2 (CE Controlled Timing)(1,5)

ADDRESS

CE

R/W (9)

DATAIN

tAS(6)

tWC

tAW

tEW (2)

tDW

tWR

tDH

2746 drw 10

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL.

3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.

4. During this period, the I/O pins are in the output state, and input signals must not be applied.

5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. Timing depends on which enable signal is de-asserted first, CE or OE.

8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed

on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified tWP.

9. R/W for either upper or lower byte.

61.412

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