IDT70261SL データシートの表示（PDF） - Integrated Device Technology

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IDT70261SL

HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT

Integrated Device Technology 

HIGH-SPEED

IDT70261S/L

16K x 16 DUAL-PORT

STATIC RAM WITH INTERRUPT

Features

◆ True Dual-Ported memory cells which allow simultaneous

access of the same memory location

◆ High-speed access

– Commercial: 15/20/25/35/55ns (max.)

– Industrial 20/25ns (max.)

◆ Low-power operation

– IDT70261S

Active: 750mW (typ.)

Standby: 5mW (typ.)

– IDT70261L

Active: 750mW (typ.)

Standby: 1mW (typ.)

◆ Separate upper-byte and lower-byte control for multiplexed

bus compatibility

◆ IDT70261 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

◆ M/S = H for BUSY output flag on Master,

M/S = L for BUSY input on Slave

◆ Busy and Interrupt Flags

◆ On-chip port arbitration logic

◆ Full on-chip hardware support of semaphore signaling

between ports

◆ Fully asynchronous operation from either port

◆ TTL-compatible, single 5V (±10%) power supply

◆ Available in 100-pin Thin Quad Flatpack

◆ Industrial temperature range (-40OC to +85OC) is available

for selected speeds

Functional Block Diagram

R/WL

UBL

R/WR

UBR

LBL

CEL

OEL

LBR

CER

OER

I/O8L-I/O15L

I/O0L-I/O7L

BUSYL(1,2)

I/O

Control

I/O

Control

A13L

A0L

Address

Decoder

MEMORY

ARRAY

14

14

CEL

OEL

R/WL

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

SEML

INTL (2)

M/S

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY and INT outputs are non-tri-stated push-pull.

Address

Decoder

CER

OER

R/WR

1

©2009 Integrated Device Technology, Inc.

I/O8R-I/O15R

I/O0R-I/O7R

BUSYR(1,2)

A13R

A0R

SEMR

INTR(2)

3039 drw 01

JANUARY 2009

DSC 3039/10

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