IDT7025 データシートの表示（PDF） - Integrated Device Technology
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IDT7025 Datasheet PDF : 20 Pages
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IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
tWC
ADDR"A"
tAS(3)
INTERRUPT SET ADDRESS (2)
CE"A"
tWR(4)
W R/ "A"
INT"B"
ADDR"B"
CE"B"
tINS(3)
tAS (3)
tRC
INTERRUPT CLEAR ADDRESS(2)
2683 drw 17
OE"B"
tINR(3)
INT"B"
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Flag truth table.
3. Timing depends on which enable signal ( CE or R/W ) is asserted last.
4. Timing depends on which enable signal ( CE or R/W ) is de-asserted first.
2683 drw 18
TRUTH TABLES
TRUTH TABLE III — INTERRUPT FLAG(1)
W R/ L
L
X
X
X
Left Port
CEL OEL A0L-A12L INTL
L
X 1FFF X
X
X
X
X
X
X
X
L(3)
L
L
1FFE H(2)
R/WR
X
X
L
X
Right Port
CER OER A0R-A12R INTR
X
X
X
L(2)
L
L
1FFF H(3)
L
X 1FFE X
X
X
X
X
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
2683 tbl 17
6.16
15
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