IDT7025 データシートの表示（PDF） - Integrated Device Technology

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IDT7025

HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7025S/L

HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE(6)

Symbol

Parameter

BUSY TIMING (M/S = VIH)

tBAA

BUSY Access Time from Address Match

tBDA

BUSY Disable Time from Address Not Matched

tBAC

BUSY Access Time from Chip Enable Low

tBDC

BUSY Disable Time from Chip Enable High

tAPS

Arbitration Priority Set-up Time(2)

tBDD

BUSY Disable to Valid Data(3

tWH

Write Hold After BUSY(5)

BUSY TIMING (M/S = VIL)

tWB

BUSY Input to Write(4)

tWH

Write Hold After BUSY(5)

IDT7025X15

Com'l Only

Min. Max.

— 15

— 15

— 15

— 15

5

—

— 18

12 —

0

—

12 —

PORT-TO-PORT DELAY TIMING

tWDD

Write Pulse to Data Delay(1)

tDDD

Write Data Valid to Read Data Delay(1)

— 30

— 25

IDT7025X17

Com'l Only

Min. Max.

— 17

— 17

— 17

— 17

5

—

— 18

13 —

0

—

13 —

— 30

— 25

IDT7025X20

Min. Max.

— 20

— 20

— 20

— 17

5

—

— 30

15 —

0

—

15 —

— 45

— 35

IDT7025X25

Min. Max. Unit

— 20 ns

— 20 ns

— 20 ns

— 17 ns

5

— ns

— 30 ns

17 — ns

0

— ns

17 — ns

— 50 ns

— 35 ns

Symbol

Parameter

BUSY TIMING (M/S = VIH)

tBAA

BUSY Access Time from Address Match

tBDA

BUSY Disable Time from Address Not Matched

tBAC

BUSY Access Time from Chip Enable Low

tBDC

BUSY Disable Time from Chip Enable High

tAPS

Arbitration Priority Set-up Time(2)

tBDD

BUSY Disable to Valid Data(3)

tWH

Write Hold After BUSY(5)

IDT7025X35

Min. Max.

IDT7025X55

Min. Max.

IDT7025X70

Mil. Only

Min. Max. Unit

—

20

—

45

—

45 ns

—

20

—

40

—

40 ns

—

20

—

40

—

40 ns

—

20

—

35

—

35 ns

5

—

5

—

5

— ns

—

35

—

40

—

45 ns

25

—

25

—

25

— ns

BUSY TIMING (M/S = VIL)

tWB

BUSY Input to Write(4)

tWH

Write Hold After BUSY(5)

0

—

0

—

0

— ns

25

—

25

—

25

— ns

PORT-TO-PORT DELAY TIMING

tWDD

Write Pulse to Data Delay(1)

tDDD

Write Data Valid to Read Data Delay(1)

—

60

—

80

—

95 ns

—

45

—

65

—

80 ns

NOTES:

2683 tbl 15

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH)" or "Timing Waveform

of Write With Port-To-Port Delay (M/S = VIH)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual), or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited pn Port "B" during contention with Port "A".

5. To ensure that a write cycle is completed on Port "B" after contention with Port "A".

6. "X" in part numbers indicates power rating (S or L).

6.16

12

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