IDT2309B データシートの表示（PDF） - Integrated Device Technology
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IDT2309B Datasheet PDF : 10 Pages
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IDT2309B
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
S2
S1
CLKA
CLKB
CLKOUT(2)
Output Source PLL Shut Down
L
L
Tri-State
Tri-State
Driven
PLL
N
L
H
Driven
Tri-State
Driven
PLL
N
H
L
Driven
Driven
Driven
REF
Y
H
H
Driven
Driven
Driven
PLL
N
NOTES:
1. H = HIGH Voltage Level.
L = LOW Voltage Level
2. This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew between the REF and the output.
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol
Parameter
Conditions
Min.
Max.
Unit
VIL
Input LOW Voltage Level
—
0.8
V
VIH
Input HIGH Voltage Level
2
—
V
IIL
Input LOW Current
VIN = 0V
—
50
µA
IIH
Input HIGH Current
VIN = VDD
—
100
µA
VOL
Output LOW Voltage
Standard Drive
IOL = 8mA
—
0.4
V
High Drive
IOL = 12mA (-1H)
VOH
Output HIGH Voltage
Standard Drive
IOH = -8mA
2.4
—
V
High Drive
IOH = -12mA (-1H)
IDD_PD
Power Down Current
REF = 0MHz (S2 = S1 = H)
—
12
µA
IDD
Supply Current
Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND
—
32
mA
OPERATING CONDITIONS - COMMERCIAL
Symbol
VDD
TA
CL
CIN
Parameter
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance < 100MHz
Load Capacitance 100MHz - 133MHz
Input Capacitance
Min.
Max.
Unit
3
3.6
V
0
70
°C
—
30
pF
—
10
—
7
pF
SWITCHING CHARACTERISTICS (2309B-1) - COMMERCIAL(1,2)
Symbol
Parameter
Conditions
Min.
t1
Output Frequency
10pF Load
10
30pF Load
10
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
t3
Rise Time
Measured between 0.8V and 2V
—
t4
Fall Time
Measured between 0.8V and 2V
—
t5
Output to Output Skew
All outputs equally loaded
—
t6A
Delay, REF Rising Edge to CLKOUT Rising Edge(2) Measured at VDD/2
—
t6B
Delay, REF Rising Edge to CLKOUT Rising Edge(2) Measured at VDD/2 in PLL bypass mode (IDT2309B only)
1
t7
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
tJ
Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
—
tLOCK PLL Lock Time
Stable power supply, valid clock presented on REF pin
—
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
3
Typ. Max. Unit
— 133 MHz
— 100
50 60 %
— 2.5 ns
— 2.5 ns
— 250 ps
0 ±350 ps
5 8.7 ns
0 700 ps
50 175 ps
—
1 ms
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