570AILF データシートの表示（PDF） - Integrated Circuit Systems
部品番号
コンポーネント説明
一致するリスト
570AILF Datasheet PDF : 9 Pages
| |||
Pin Assignment
S1
VDD
GND
ICLK
1
8 CLK/2
2
7 CLK
3
6 S0
4
5 FBIN
8 pin (150 mil) SOIC
ICS570
Multiplier and Zero Delay Buffer
Clock Multiplier Decoding Table
(Multiplies Input clock by amount shown)
FBIN from CLK FBIN from CLK/2
ICS570B (3.3 V)
ICS570A (5.0 V)
S1 S0 CLK CLK2 CLK CLK2 ICLK Input Range FB from CLK/2* ICLK Input Range FB from CLK/2*
#1 #6 pin #7 pin #8 pin #7 pin #8
00
Power Down and Tri-State
0 M x3
x1.5
x6
x3
0 1 x4
x2
x8
x4
M 0 x8
x4
x16
x8
M M x6
x3
x12
x6
M 1 x10
x5
x20
x10
1 0 x1
/2
x2
x1
1 M x16
x8
x32
x16
1 1 x2
x1
x4
x2
0 = connect directly to ground
M = leave unconnected (self-biases to VDD/2)
1 = connect directly to VDD
*Input range with CLK feedback is double that for CLK/2
-
3.75 to 28
2.75 to 19
2.5 to 9.5
2.5 to 12.5
2.5 to 7.5
11 to 75
2.5 to 5
5.5 to 37.5
-
2.5 to 25
2.5 to 19
2.5 to 9.5
2.5 to 12.5
2.5 to 7.5
5 to 75
2.5 to 5
2.5 to 37.5
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
S1
VDD
GND
ICLK
FBIN
S0
CLK
CLK/2
Pin
Type
Input
Power
Power
Input
Input
Input
Output
Output
Pin Description
Select 1 for output clock. Connect to GND, VDD, or float per decoding table above.
Connect to +3.3 V (ICS570B). Connect to +5.0 V (ICS570A).
Connect to ground.
Reference clock input.
Feedback clock input.
Select 0 for output clock. Connect to GND, VDD, or float per decoding table above.
Clock output per table above.
Clock output per table above. Low skew divide by two of pin 7 clock.
MDS 570 I
2
Revision 030905
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
Share Link: 