HSP45116AVC-52Z データシートの表示（PDF） - Intersil
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HSP45116AVC-52Z Datasheet PDF : 19 Pages
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HSP45116A
AC Electrical Specifications
VCC = 5.0V ±5%, TA = 0°C to +70°C (Note 5) (Continued)
52.6MHz (-52)
PARAMETER
SYMBOL
NOTES
MIN
MAX
UNITS
Setup Time WR to CLK
tWC
7
10
-
ns
Setup Time MOD0-1 to CLK
tMCS
10
-
ns
Hold Time MOD0-1 from CLK
tMCH
0
-
ns
Setup Time PACI to CLK
tPCS
10
-
ns
Hold Time PACI from CLK
tPCH
0
-
ns
Setup Time ENPHREG, ENCFREG, ENOFREG,
ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI,
ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD to
CLK
tECS
10
-
ns
Hold Time ENPHREG, ENCFREG, ENOFREG,
ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI,
ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD
from CLK
tECH
0
-
ns
Setup Time RIN0-18, IMIN0-18 to CLK
tDS
10
-
ns
Hold Time RIN0-18, IMIN0-18 from CLK
tDH
0
-
ns
CLK to Output Delay RO0-19, IO0-19
tDO
-
12
ns
CLK to Output Delay DET0-1
tDEO
-
12
ns
CLK to Output Delay PACO
tPO
-
12
ns
CLK to Output Delay TICO
tTO
-
12
ns
Output Enable Time OER, OEI, OEREXT, OEIEXT
tOE
-
8
ns
Output Enable Time OUTMUX0-1
tMD
-
14
ns
Output Disable Time
tOD
6
-
8
ns
Output Rise, Fall Time
tRF
6
-
4
ns
NOTES:
5. AC tests performed with CL = 40pF, IOL = 2.0mA, and IOH = -0.4mA. Input reference level for CLK = 2.0V, all other inputs 1.5V. Test
VIH = 3.0V, VIHC = 4.0V, VIL = 0V; VOH ≥1.5V, VOL ≤ 1.5V.
6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes.
7. Applicable only when outputs are being monitored and ENCFREG, ENPHREG or ENTIREG is active. WR is always asynchronous when RND
is active.
AC Test Load Circuit
DUT
S1
CL (NOTE)
SWITCH S1 OPEN FOR ICCSB AND ICCOP
NOTE: Test head capacitance.
±
IOH
1.5V
IOL
EQUIVALENT CIRCUIT
16
FN4156.4
May 7, 2007
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