HSP43124PC-33 データシートの表示（PDF） - Intersil

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HSP43124PC-33

Serial I/O Filter

Intersil 

HSP43124

DIN

SYNCIN

SYNCMX

MXIN

INPUT FORMATTER

FILTER COMPUTE ENGINE

OUTPUT

VARIABLE LENGTH

SHIFT REGISTER

# BITS†

MSB F/2†

(8-24-BITS)

FORMAT†

57

INPUT

HOLDING

REG

MIX FACTOR

HOLDING

REG

MUX

SYNCIN

SERIAL

MULTIPLIER

SYNCMX

MIX

SEL†

MXIN

M

U

48 X

ROUND/ 24 REGISTER

SATURATE

FILE

25

+

CONTROL

† PARAMETERS †

FILT EN†

MULTIPLY/

ACCUMULATOR

R

+E

G

FORMATTER

MSB F/L†

FCLK†

CLKOUT

# BITS†

ROUND/

SATURATE

32

MUX

ROUND†

DECIMATION FORMAT†

RATE† GAIN COR†

SYNCOUT

CLKOUT

DOUT

WEAVER

MODULATOR

ROM

VARIABLE LENGTH

SHIFT REGISTER

(8 TO 24 BITS)

# BITS†

FORMAT†

CONTROL

# HBs†

FIR SYM†

HALFBAND

COEFFICIENT

ROM

COEFFICIENT

RAM

RD EN†

FILTER LENGTH†

RAM ACCESS †

A0-2

C0-7

WR

RD

FSYNC

FCLK

SCLK

†Indicates configuration control word data parameter.

FIGURE 1. SERIAL FILTER BLOCK DIAGRAM

Functional Descriptions

The HSP43124 is a high performance digital filter designed to

process a serial input data stream. A second serial interface is

provided for mix factor inputs, which are multiplied by the input

samples as shown in Figure 1. The multiplier result is passed

to the Filter Compute Engine for processing.

The Filter Compute Engine centers around a single

multiply/accumulator (MAC). The MAC performs the sum-of-

products required by a particular filter configuration. The

processing rate of the MAC is determined by the filter clock,

FCLK. Increasing FCLK relative to the input sample rate

increases the length of filter that can be realized.

The filtered results are passed to the Output Formatter where

they are rounded or truncated to a user defined bit width. The

Output Formatter then generates the timing and

synchronization signals required to serially transmit the data

to an external device.

Filter Configuration

The HSP43124 is configured for operation by loading a set of

eight control registers. These registers are written through a

bidirectional interface which is also used for reading the

control registers. The interface consists of an 8-bit data bus,

C0-7, a 3-bit address bus, A0-2, and read/write lines, RD and

WR. The address map for the control registers is shown in

Table 1.

Data is written to the configuration control registers on the

falling edge of the WR input. This requires that the address,

A0-2, and data, C0-7, be stable and valid on the falling edge

of the WR, as shown in Figure 2. NOTE: WR should not be

active low when RD is active low.

Data is read from the configuration control registers on the

falling edge of the RD input. The contents of a particular

register are accessed by setting up an address, A0-2, to the

falling edge of RD as shown in Figure 2. The data is output on

C0-7. The data on C0-7 remains valid until RD returns HIGH,

at which point the C0-7 bus is Three-Stated and functions as

an input. For proper operation, the address on A0-2 must be

held until RD returns “high” as shown in Figure 2. NOTE: RD

should not be active low when WR is active low.

WRITE TIMING

WR

A0-2

C0-7

RD

A0-2

C0-7

READ TIMING

FIGURE 2. READ/WRITE TIMING

4

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