HM-65642 データシートの表示（PDF） - Intersil
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HM-65642 Datasheet PDF : 7 Pages
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HM-65642
Low Voltage Data Retention
Intersil CMOS RAMs are designed with battery backup in
mind. Data Retention voltage and supply current are guaran-
teed over the operating temperature range. The following
rules ensure data retention:
1. The RAM must be kept disabled during data retention. This is ac-
complished by holding the E2 pin between -0.3V and GND.
2. During power-up and power-down transitions, E2 must be held
between -0.3V and 10% of VCC.
3. The RAM can begin operating one TAVAX after VCC reaches the
minimum operating voltage of 4.5V.
VCC
4.5V
VIH
E2
VCCOR
DATA RETENTION MODE
TAVAX
GND
Read Cycles
A
Q
FIGURE 1. DATA RETENTION
TAVAX (1)
ADDRESS 1
TAVQV (2)
ADDRESS 2
TAXQX (12)
DATA 1
DATA 2
FIGURE 2. READ CYCLE I: W, E2 HIGH; G, E1 LOW
TAVAX (1)
A
TAVQV (2)
E1
TE1LQV (3)
TE1LQX (6)
E2
TE2HQV (4)
TE2HQX (7)
G
TGLQV (5)
TGLQX (8)
Q
TE1HQZ (9)
TE2LQZ (10)
TGHQZ (11)
FIGURE 3. READ CYCLE II: W HIGH
6-5
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