HFA3824A データシートの表示（PDF） - Intersil

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HFA3824A

Direct Sequence Spread Spectrum Baseband Processor

Intersil 

HFA3824A

The procedure for setting the ADC references to

accommodate various input signal voltage levels is to set the

reference voltages so that the ADC calibration circuit is oper-

ating at half scale. This leaves the maximum amount of

adjustment room for circuit tolerances.

Figure 8 illustrates the suggested interface configuration for

the ADCs and the reference circuits.

I

0.01µF

Q

3.9K 0.01µF

2V

8.2K

9.1K

IIN

0.01µF

QIN

VREFP

0.01µF

VREFN

HFA3824A

FIGURE 8. INTERFACES

ADC Calibration Circuit and Registers

The ADC compensation or calibration circuit is designed to

optimize ADC performance for the I and Q inputs by main-

taining the full 3-bit resolution of the outputs. There are two

registers (CR 11 AD_CAL_POS and CR 12 AD_CAL_NEG)

that set the parameters for the internal I and Q ADC calibra-

tion circuit.

Both I and Q ADC outputs are monitored by the ADC calibra-

tion circuit and if either has a full scale value, a 24-bit accu-

mulator is incremented as defined by parameter

AD_CAL_POS. If neither has a full scale value, the accumu-

lator is decremented as defined by parameter

AD_CAL_NEG.

A loop gain reduction is accomplished by using only the 5

MSBs out of the 24 bits to drive a D/A converter that adjusts

the ADCs reference. The compensation adjustment is

updated at 2kHz rate for a 2 MBPS operation. The ADC cali-

bration circuit is only intended to remove slow component

variations.

The ratio of the values from the two registers CR11 and

CR12 set the probability that either the I or Q ADC converter

will be at the saturation. The probability is set by

(AD_CAL_POS)/(AD_CAL_NEG).

This also sets the levels so that operation with either NOISE

or DPSK is approximately the same. It is assumed that the

RF and IF sections of the receiver have enough gain to

cause limiting on thermal noise. This will keep the levels at

the ADC approximately same regardless of whether signal is

present or not.

The ADC calibration voltage is automatically held during

transmit in half duplex operation.

The ADC calibration circuit operation can be defined through

CR 1, bits 1 and 0. Table 3 illustrates the possible

configurations.

CR 1

BIT 0

0

0

1

1

TABLE 3. ADC CALIBRATION

CR 1

BIT 1

ADC CALIBRATION CIRCUIT

CONFIGURATION

0 Automatic real time adjustment of reference.

1 Reference set at mid scale.

0 Reference held at most recent value.

1 Reference set at mid scale.

RSSI ADC Interface

The Receive Signal Strength Indication (RSSI) analog signal is

input to a 6-bit ADC, indicating 64 discrete levels of received

signal strength. This ADC measures a DC voltage, so its input

must be DC coupled. Pin 16 (VREFP) sets the reference for the

RSSI ADC converter. VREFP is common for the I and Q and

RSSI ADCs. The RSSI signal is used as an input to the pro-

grammable Clear Channel Assessment algorithm of the

HFA3824A. The RSSI ADC output is stored in an 8-bit register

(CR10) and it is updated at the symbol rate for access by the

external processor to assist in network management.

The interface specifications for the RSSI ADC are listed in

Table 4 below (VREFP = 1.75V).

TABLE 4. RSSI ADC SPECIFICATIONS

PARAMETER

MIN

TYP

MAX

Full Scale Input Voltage

-

-

1.15

Input Bandwidth (0.5dB)

1MHz

-

-

Input Capacitance

-

7pF

-

Input Impedance (DC)

1M

-

-

Test Port

The HFA3824A provides the capability to access a number

of internal signals and/or data through the Test port, pins

TEST 0-7. In addition pin 1 (TEST_CK) is an output clock

that can be used in conjunction with the data coming from

the test port outputs. The test port is programmable through

configuration register (CR5).

There are 9 test modes assigned to the PRISM test port

listed in Test Modes Table 5.

TABLE 5. TEST MODES

MODE DESCRIPTION TEST_CLK

TEST (7:0)

0 Normal

Operation

TXCLK

CRS, ED, “000”, Initial

Detect, Reserved (1:0)

1 Correlator Test TXCLK

Mode

Mag (7:0)

2 Frequency Test DCLK

Mode

Frq Reg (7:0)

3 Phase Test

Mode

DCLK

Phase (7:0)

4 NCO Test Mode DCLK

NCO Phase Accum Reg

5 SQ Test Mode LoadSQ

SQ2 (15:8) Phase

Variance

6 Bit Sync Test

Mode 1

RXCLK

Bit Sync Accum (7:0)

2-110

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