HB54A5129F1U(2003) データシートの表示（PDF） - Elpida Memory, Inc
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HB54A5129F1U Datasheet PDF : 16 Pages
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HB54A5129F1U-B75B/10B
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Minimum active to precharge time
30
(tRAS)
0 0 1 0 1 1 0 1 2D
-B75B
45ns
-10B
0 0 1 1 0 0 1 0 32
50ns
31
Module rank density
1 0 0 0 0 0 0 0 80
1 rank
512MB
32
33
E34
O35
L 36 to 40
Address and command setup time
before clock (tIS)
1
-B75B
-10B
1
Address and command hold time after
clock (tIH)
1
-B75B
-10B
1
Data input setup time before clock
(tDS)
0
-B75B
-10B
0
Data input hold time after clock (tDH)
-B75B
0
-10B
0
Superset information
0
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
90
B0
90
B0
50
60
50
60
00
0.9ns*5
1.1ns*5
0.9ns*5
1.1ns*5
0.5ns*5
0.6ns*5
0.5ns*5
0.6ns*5
Future use
41
42
43
44
45
46 to 61
62
63
64
65 to 71
72
73
74
75
Active command period (tRC)
-B75B
0 1 0 0 0 0 0 1 41
-10B
0 1 0 0 0 1 1 0 46
Auto refresh to active/
Auto refresh command cycle (tRFC) 0 1 0 0 1 0 1 1 4B
-B75B
P -10B
0 1 0 1 0 0 0 0 50
SDRAM tCK cycle max. (tCK max.) 0 0 1 1 0 0 0 0 30
Dout to DQS skew
-B75B
0 0 1 1 0 0 1 0 32
r -10B
0 0 1 1 1 1 0 0 3C
Data hold skew (tQHS)
-B75B
0 1 1 1 0 1 0 1 75
o -10B
1 0 1 0 0 0 0 0 A0
Superset information
0 0 0 0 0 0 0 0 00
SPD revision
d Checksum for bytes 0 to 62
-B75B
-10B
0 0 0 0 0 0 0 0 00
0 0 1 1 0 0 1 1 33
1 1 1 1 1 0 0 0 F8
Manufacturer’s JEDEC ID code
0 0 0 0 0 1 1 1 07
u Manufacturer’s JEDEC ID code
0 0 0 0 0 0 0 0 00
Manufacturing location
× × × × × × × × ××
c Module part number
Module part number
t Module part number
0 1 0 0 1 0 0 0 48
0 1 0 0 0 0 1 0 42
0 0 1 1 0 1 0 1 35
65ns*5
70ns*5
75ns*5
80ns*5
12ns*5
500ps*5
600ps*5
750ps*5
1000ps*5
Future use
Initial
51
248
HITACHI
*2 (ASCII-8bit
code)
H
B
5
76
Module part number
0 0 1 1 0 1 0 0 34
4
77
Module part number
0 1 0 0 0 0 0 1 41
A
78
Module part number
0 0 1 1 0 1 0 1 35
5
79
Module part number
0 0 1 1 0 0 0 1 31
1
Data Sheet E0191H40 (Ver. 4.0)
6
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