HB54A5129F1U(2003) データシートの表示（PDF） - Elpida Memory, Inc
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HB54A5129F1U Datasheet PDF : 16 Pages
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DATA SHEET
512MB Registered DDR SDRAM DIMM
HB54A5129F1U-B75B/10B (64M words × 72 bits, 1 Rank) Description
The HB54A5129F1U is a 64M × 72 × 1 rank Double
Data Rate (DDR) SDRAM Module, mounting 18 pieces
of 256Mbits DDR SDRAM sealed in TSOP package, 1
piece of PLL clock driver, 2 pieces of register driver
Eand 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD). Read and write operations are
performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2-bit
Oprefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. An outline of the products is
184-pin socket type package (dual lead out).
L Therefore, it makes high density mounting possible
without surface mount technology. It provides common
data inputs and outputs. Decoupling capacitors are
Product mounted beside each TSOP on the module board.
Features
• 184-pin socket type package (dual lead out)
Outline: 133.35mm (Length) × 30.48mm (Height) ×
4.00mm (Thickness)
Lead pitch: 1.27mm
• 2.5V power supply (VCC/VCCQ)
• SSTL-2 interface for all inputs and outputs
• Clock frequency: 133MHz/125MHz (max.)
• Data inputs and outputs are synchronized with DQS
• 4 banks can operate simultaneously and
independently (Component)
• Burst read/write operation
• Programmable burst length: 2, 4, 8
Burst read stop capability
• Programmable burst sequence
Sequential
Interleave
• Start addressing capability
Even and Odd
• Programmable /CAS latency (CL): 3, 3.5
• 8192 refresh cycles: 7.8µs (8192/64ms)
• 2 variations of refresh
Auto refresh
Self refresh
Document No. E0191H40 (Ver. 4.0)
Date Published March 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory,Inc. 2001-2003
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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