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GS1582(2007) データシートの表示(PDF) - Gennum -> Semtech

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GS1582 Datasheet PDF : 114 Pages
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GS1582 Data Sheet
Table 2-3: AC Electrical Characteristics (Continued)
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter
Symbol Conditions
Min
Typ
Max Units
Notes
Mismatch in rise/fall time
Δtr,Δtf
35
ps
Duty Cycle Distortion
1
5
%
5
Overshoot
SD/HD=0
5
10
%
5
SD/HD=1
3
8
%
5
Output Return Loss
ORL
5 MHz - 1.485 GHz
18
dB
6
Serial Output Intrinsic Jitter
tOJ
Pseudorandom and
35
80
ps
2
SMPTE Colour Bars
HD signal
tOJ
Pseudorandom and
100
200
ps
3
SMPTE Colour Bars
SD signal
GSPI
GSPI Input Clock Frequency fSCLK
50% levels
10
MHz
3.3V or 1.8V operation
GSPI Input Clock Duty Cycle DCSCLK
40
50
60
%
GSPI Input Data Setup Time
1.5
ns
GSPI Input Data Hold Time
1.5
ns
GSPI Output Data Hold Time
15pF load
1.5
ns
CS low before SCLK rising
50% levels
1.5
ns
edge
3.3V or 1.8V operation
Time between end of
50% levels
37.1
ns
command word (or data in
3.3V or 1.8V operation
Auto-Increment mode) and
the first SCLK of the following
data word - write cycle
Time between end of
50% levels
148.4
ns
command word (or data in
3.3V or 1.8V operation
Auto-Increment mode) and
the first SCLK of the following
data word - read cycle
CS high after SCLK rising
50% levels
37.1
ns
edge
3.3V or 1.8V operation
NOTES:
1. See ’Device Reset’ on page 107, Figure 4-33.
2. Alignment Jitter = measured from 100kHz to 148.5MHz
3. Alignment Jitter = measured from 1kHz to 27MHz
4. Input setup and hold time is dependent on the rise and fall time on the parallel input. Parallel clock and data with rise time or fall time
greater than 500ps require larger setup and hold times.
5. Single Ended into 75Ω external load.
6. ORL depends on board design. The GS1582 achieves this specification on Gennum’s evaluation boards.
40117 - 1 November 2007
20 of 114

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