GS1582(2007) データシートの表示（PDF） - Gennum -> Semtech

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GS1582
(Rev.:2007)

Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleaner™

Gennum -> Semtech 

GS1582 Data Sheet

Table 1-1: Pin Descriptions (Continued)

Pin

Number

Name

Timing

Type Description

J4

AIN_5/6

Synchronous Input Serial Audio Input; Channels 5 and 6.

with ACLK_2

J5

WCLK_2

Clock

Input 48kHz word clock for Audio Group 2.

J6

AIN_1/2

Synchronous Input Serial Audio Input; Channels 1 and 2.

with ACLK_1

J7

WCLK_1

Clock

Input 48kHz word clock for Audio Group 1.

J9

SDOUT_TDO

Synchronous Output COMMUNICATION SIGNAL OUTPUT

with

Signal levels are LVCMOS/LVTTL compatible.

SCLK_TCK

Serial Data Output / Test Data Output

Host Mode (JTAG/HOST = LOW)

This pin operates as the host interface serial output, used to read status

and configuration information from the internal registers of the device.

JTAG Test Mode (JTAG/HOST = HIGH)

This pin is used to shift test results and operates as the JTAG test data

output, TDO.

NOTE: If the host interface is not being used leave this pin

unconnected.

IO_VDD = 3.3V

Drive Strength = 12mA

IO_VDD = 1.8V

Drive Strength = 4mA

J10

SCLK_TCK

Non

Input COMMUNICATION SIGNAL INPUT

Synchronous

Signal levels are LVCMOS/LVTTL compatible.

Serial Data Clock / Test Clock.

Host Mode (JTAG/HOST = LOW)

SCLK_TCK operates as the host interface burst clock, SCLK.

Command and data read/write words are clocked into the device

synchronously with this clock.

JTAG Test Mode (JTAG/HOST = HIGH)

This pin is the TEST MODE START pin, used to control the operation of

the JTAG test clock, TCK.

NOTE: If the host interface is not being used, tie this pin HIGH.

40117 - 1 November 2007

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