AN-6920MR データシートの表示（PDF） - Fairchild Semiconductor
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AN-6920MR
Fairchild Semiconductor
AN-6920MR Datasheet PDF : 17 Pages
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AN-6920
APPLICATION NOTE
Final Schematic of Design Example
This section summaries the final design example. The key
system specifications are summarized in Table 1 and the key
design parameters are summarized in Table 2. The final
schematic is in Figure 21. To have enough hold-up time for
VDD during startup, a two-stage circuit is used for VDD. To
maximize the efficiency, the synchronous rectification using
Fairchild’s FAN6204 is used for the secondary rectifier.
Table 1. System Specifications
Input
Input Voltage Range
Line Frequency Range
Output
Output Voltage (Vo)
Output Power (Po)
90~264VAC
47~63Hz
19V
90W
Table 2. Key Design Parameters
PFC Stage
PFC Inductor (LBOOST)
450µH
Turns of PFC Inductor (NBOOST)
44T
Turns of ZCD Auxiliary Winding (NZCD)
Minimum Switching Frequency (fS.PFCmin)
PWM Stage
8T
40kHz
Turns of Primary Inductor of PWM Transformer (NP) 48T
Turns of Auxiliary Winding of PWM Transformer
(NAUX)
4T
Turns of Auxiliary Winding of High-Side Driver
Transformer (NAUX.H)
3T
Turns Ratio of PWM Transformer (n)
12
Primary Inductor (LP)
Minimum Switching Frequency (fs.QRmin)
1160µH
70kHz
NBOOST
44T
DPFC
RHV
150kΩ
CINF2
470nF
NCZD
8T
RPFC3
249kΩ
D1
CINF1
330nF
RCIN1 RCIN2
1.5MΩ 1.5MΩ
CCOMP
470nF
D2
VAC
RVIN1
9.4MΩ
RVIN2
154kΩ
CVIN
2.2µF
Q1
10Ω
RG1
RCS1
0.2Ω
RPFC1
9.4MΩ
RPFC2
78.7kΩ
CO.PFC
100µF
RCZD 47.5kΩ
IC1: FAN6920
1 RANGE
2 COMP
3 INV
4 CSPFC
5 CSPWM
6 OPFC
7 VDD
8 OPWM
HV 16
NC 15
ZCD 14
VIN 13
RT 12
FB 11
DET 10
GND 9
RRT
3.7kΩ
CRT
1nF
NTC
CFB
47nF
CDD
68µF
DBOOST
CBOOT
0.1µF
DAUX.H
NAUX.H
3T
IC2: FAN7382
1 VCC
VB 8
2 HIN
HO 7
3 LIN
VS 6
4 COM LO 5
Q2
RG2
10Ω
DR1
DR2
NP
48T
Q3
RG3
10Ω
RCS2
0.27Ω
DAUX
NA
3T
RDET1
47.5kΩ
RDET2
8.25kΩ
NS
4T
COUT1
820µF/25V
LOUT
47nH
COUT2
820µF/25V
+
RSN CSN
16Ω 2.2nF
VOUT
19V
Q4
RLPC1
220kΩ
3
5
GATE VDD
FAN6204
8 LPC
RES 7
RLPC1
8.8kΩ
AGND
126
GND
4
IC3: FAN6204
-
RES1
47.5kΩ
RES2
12kΩ
RBIAS
330Ω
IC4: PC817
RO1
66.5kΩ
RF
CF
1.2kΩ 10nF
IC5: KA431
RO2
10kΩ
Figure 21. Final Schematic of Design Example
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
14
www.fairchildsemi.com
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