EPCS16 データシートの表示（PDF） - Altera Corporation

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EPCS16

Serial Configuration Devices

Altera Corporation 

Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet

3–5

Active Serial FPGA Configuration

Figure 3–3. Altera FPGA Configuration in AS Mode (Serial Configuration Device Programmed by APU or Third-Party

Programmer) (Note 1), (4)

VCC (1) VCC (1) VCC (1)

10 k 10 k

10 k

Serial

Configuration

Device (2)

Altera FPGA

CONF_DONE

nSTATUS

nCONFIG

nCEO

N.C.

nCE

MSEL[]

(3)

DATA

DCLK

nCS

ASDI

DATA0

DCLK

nCSO

ASDO

Notes to Figure 3–3:

(1) For the VCC value, refer to the respective FPGA family handbook Configuration chapter.

(2) Serial configuration devices cannot be cascaded.

(3) Connect the FPGA MSEL[] input pins to select the AS configuration mode. For details, refer to the respective FPGA family chapter in the

Configuration Handbook.

(4) For more information about configuration pin I/O requirements in an AS scheme for an Altera FPGA, refer to the respective FPGA family handbook

Configuration chapter..

The FPGA acts as the configuration master in the configuration flow and provides the

clock to the serial configuration device. The FPGA enables the serial configuration

device by pulling the nCS signal low via the nCSO signal (refer to Figure 3–2 and

Figure 3–3). Subsequently, the FPGA sends the instructions and addresses to the serial

configuration device via the ASDO signal. The serial configuration device responds to

the instructions by sending the configuration data to the FPGA’s DATA0 pin on the

falling edge of DCLK. The data is latched into the FPGA on the next DCLK signal’s

falling edge.

1 Before the FPGA enters configuration mode, ensure that VCC of the EPCS is ready. If it

is not, you must hold nCONFIG low until all power rails of EPCS are ready.

The FPGA controls the nSTATUS and CONF_DONE pins during configuration in AS

mode. If the CONF_DONE signal does not go high at the end of configuration or if the

signal goes high too early, the FPGA will pulse its nSTATUS pin low to start

reconfiguration. Upon successful configuration, the FPGA releases the CONF_DONE

pin, allowing the external 10-k resistor to pull this signal high. Initialization begins

after the CONF_DONE goes high. After initialization, the FPGA enters user mode.

f For more information about configuring the FPGAs in AS mode or other

configuration modes, refer to the Configuration chapter in the appropriate device

handbook.

© December 2009 Altera Corporation

Configuration Handbook (Complete Two-Volume Set)

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