DS21448 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS21448

3.3V E1/T1/J1 Quad Line Interface

Dallas Semiconductor -> Maxim Integrated 

DS21448 3.3V T1/E1/J1 Quad Line Interface

LIST OF FIGURES

Figure 1-1. Block Diagram ....................................................................................................................... 5

Figure 1-2. Receive Logic Detail.............................................................................................................. 6

Figure 1-3. Transmit Logic Detail............................................................................................................. 6

Figure 4-1. Serial Port Operation for Read Access (R = 1) Mode 1 ........................................................15

Figure 4-2. Serial Port Operation for Read Access (R = 1) Mode 2 ........................................................16

Figure 4-3. Serial Port Operation for Read Access (R = 1) Mode 3 ........................................................16

Figure 4-4. Serial Port Operation for Read Access (R = 1) Mode 4 ........................................................16

Figure 4-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2 .............................................17

Figure 4-6. Serial Port Operation for Write Access (R = 0) Modes 3 and 4 .............................................17

Figure 7-1. Basic Interface......................................................................................................................36

Figure 7-2. Protected Interface Using Internal Receive Termination .......................................................37

Figure 7-3. Protected Interface Using External Receive Termination......................................................38

Figure 7-4. Dual Connector-Protected Interface Using Receive Termination ..........................................39

Figure 8-5. E1 Transmit Pulse Template ................................................................................................40

Figure 8-6. T1 Transmit Pulse Template.................................................................................................41

Figure 7-7. Jitter Tolerance.....................................................................................................................42

Figure 7-8. Jitter Attenuation ..................................................................................................................42

Figure 8-1. JTAG Block Diagram ............................................................................................................43

Figure 8-2. TAP Controller State Diagram ..............................................................................................44

Figure 10-1. Intel Bus Read Timing (PBTS = 0, BIS0 = 0) ......................................................................49

Figure 10-2. Intel Bus Write Timing (PBTS = 0, BIS0 = 0) ......................................................................50

Figure 10-3. Motorola Bus Timing (PBTS = 1, BIS0 = 0) ........................................................................50

Figure 10-4. Intel Bus Read Timing (PBTS = 0, BIS0 = 1) ......................................................................51

Figure 10-5. Intel Bus Write Timing (PBTS = 0, BIS0 = 1) ......................................................................52

Figure 10-6. Motorola Bus Read Timing (PBTS = 1, BIS0 = 1) ...............................................................52

Figure 10-7. Motorola Bus Write Timing (PBTS = 1, BIS0 = 1) ...............................................................52

Figure 10-8. Serial Bus Timing (BIS1 = 1, BIS0 = 0)...............................................................................53

Figure 10-9. Receive-Side Timing ..........................................................................................................54

Figure 10-10. Transmit-Side Timing .......................................................................................................55

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