DS21348 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS21348

3.3V E1/T1/J1 Line Interface

Dallas Semiconductor -> Maxim Integrated 

DS21348/Q348

PIN DESCRIPTIONS IN HARDWARE MODE (Sorted by Pin Name, DS21348T Pin

Numbering) Table 4-4b

ACRONYM PIN I/O DESCRIPTION

BIS0/

32/

BIS1

33

BPCLK

31

CES

12

DJA

8

EGL

1

ETS

2

HBE

11

HRST*

29

JAMUX

9

JAS

10

L0/L1/L2

7/

6/

5

LOOP0/

16/

LOOP1

17

I Bus Interface Select Bits 0 & 1. Used to select bus interface option.

See Table 4-1 for details.

O Back Plane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or

2.048MHz clock output that is referenced to RCLK selectable via

CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz

output.

I Receive & Transmit Clock Edge Select. Selects which RCLK

edge to update RPOS and RNEG and which TCLK edge to sample

TPOS and TNEG. CES combines TCES (CCR2.1) and RCES

(CCR2.0).

0 = update RNEG/RPOS on rising edge of RCLK; sample

TPOS/TNEG on falling edge of TCLK

1 = update RNEG/RPOS on falling edge of RCLK; sample

TPOS/TNEG on rising edge of TCLK

I Disable Jitter Attenuator.

0 = jitter attenuator enabled

1 = jitter attenuator disabled

I Receive Equalizer Gain Limit. This bit controls the sensitivity of

the receive equalizer. See Table 4-7.

I E1/T1 Select.

0 = E1

1 = T1

I Receive & Transmit HDB3/B8ZS Enable. HBE combines RHBE

(CCR2.3) and THBE (CCR2.2).

0 = enable HDB3 (E1)/B8ZS (T1)

1 = disable HDB3 (E1)/B8ZS (T1)

I Hardware Reset. Bringing HRST* low will reset the DS21348

setting all control bits to their default state of all zeros.

I Jitter Attenuator MUX. Controls the source for JACLK. See

Figure 3-1 and Table 4-10.

0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at

MCLK)

1 = JACLK sourced from internal PLL (2.048MHz at MCLK)

I Jitter Attenuator Select.

0 = place the jitter attenuator on the receive side

1 = place the jitter attenuator on the transmit side

I Transmit LIU Waveshape Select Bits 0 & 1 [H/W Mode]. These

inputs determine the waveshape of the transmitter. See Table 9-1

and Table 9-2.

I Loopback Select Bits 0 & 1 [H/W Mode]. These inputs determine

the active loopback mode (if any). See Table 4-5.

17 of 73

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