DM9103 データシートの表示（PDF） - Davicom Semiconductor, Inc.

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DM9103

10/100 Mbps 3-port Ethernet Switch Controller with PCI Interface

Davicom Semiconductor, Inc. 

DM9103

3-port switch with PCI Interface

6.1.8 Capabilities Pointer (xxxxxx34H - Cap _Ptr) ............................................................................................... 21

6.1.9 Interrupt & Latency Configuration (xxxxxx3cH - PCIINT) ............................................................................ 21

6.1.10 Device Specific Configuration Register (xxxxxx40H- PCIUSR)................................................................. 21

6.1.11 Power Management Register (xxxxxx50H~PCIPMR) ............................................................................... 22

6.1.12 Power Management Control/Status (xxxxxx54H~PMCSR)....................................................................... 23

6.2 PCI Control and Status Registers (CR).............................................................................................. 24

6.2.1 System Control Register (CR0)................................................................................................................... 25

6.2.2 Transmit Descriptor Poll Demand (CR1)..................................................................................................... 25

6.2.3 Receive Descriptor Poll Demand (CR2)...................................................................................................... 25

6.2.4 Receive Descriptor Base Address (CR3) .................................................................................................... 25

6.2.5 Transmit Descriptor Base Address (CR4) ................................................................................................... 26

6.2.6 Network Status Report Register (CR5) ....................................................................................................... 26

6.2.7 Network Operation Mode Register (CR6) ................................................................................................... 28

6.2.8 Interrupt Mask Register (CR7) .................................................................................................................... 30

6.2.9 Reserved (CR8) .......................................................................................................................................... 31

6.2.10 Management Access Register (CR9)........................................................................................................ 31

6.2.11 Reserved (CR10) ...................................................................................................................................... 32

6.2.12 Reserved (CR11) ...................................................................................................................................... 32

6.2.13 Reserved (CR12) ...................................................................................................................................... 32

6.2.14 (Reserved CR13) ...................................................................................................................................... 32

6.2.15 (Reserved CR14) ...................................................................................................................................... 32

6.2.16 Checksum Offload Control Register (CR15) ............................................................................................. 32

6.12.17 Switch Control Register (CR16) .............................................................................................................. 32

6.2.18 Per Port Index Register (CR17) ................................................................................................................ 33

6.2.19 Per Port Control Register (CR18).............................................................................................................. 33

6.2.20 Per Port Status Data Register (CR19).................................................................................................... 36

6.2.21 Per Port VLAN Tag Byte Register (CR20) ................................................................................................ 37

6.2.22 Per Port MIB counter Index Register (CR21) ......................................................................................... 37

6.2.23 MIB counter Data Register (CR22) ........................................................................................................... 38

6.2.24 VLAN priority Map Register (CR23) .......................................................................................................... 38

6.2.25 Port-based VLAN mapping table register 0 (CR24) .................................................................................. 38

6.2.26 Port-based VLAN mapping table register 1 (CR25) .................................................................................. 39

6.2.27 Port-based VLAN mapping table register 2 (CR26) .................................................................................. 39

6.2.28 Port-based VLAN mapping table register 3 (CR27) .................................................................................. 39

Preliminary datasheet

3

DM9103-DS-P02

September 26, 2007

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