CY7C955 データシートの表示（PDF） - Cypress Semiconductor
部品番号
コンポーネント説明
一致するリスト
CY7C955 Datasheet PDF : 78 Pages
| |||
PRELIMINARY
CY7C955
Receive Utopia Interface (continued)
Name
TSEN
Pin No I/O
66
Input
Description
Receive Output Enable: This output operates in conjunction with the RRDENB output.
When TSEN is HIGH and RRDENB is HIGH the Receive UTOPIA data bus (RDAT[7:0],
RPRTY, and RSOC) is three-stated. When TSEN is HIGH and RRDENB is LOW the
data bus is driven with the requested data. When TSEN is LOW the data bus will not
three-state.
Controller Interface
Name
D[7:0]
A[7:0]
ALE
Pin No
110−112
115−118
119−126
127
RDB
105
WRB
104
CSB
100
INTB
108
ALOS±
27−28
RSTB
101
VCLK
99
I/O
I/O
Input
Input
Input
Input
Input
Output
Differential In
Input
Input
Description
Data[7:0]: Bidirectional data bus used to transfer data to and from the internal config-
uration, status, and error monitoring registers.
Address[7:0]: Address bus used to select the internal register for reading or writing.
Address Latch Enable: When this input is LOW the address is latched from the A[7:0]
inputs. When this input is HIGH, the input is transparent. ALE has an integrated pull-
up resistor.
Read: This active LOW signal is used to read the internal register. The AX drives D[7:0]
when RDB and CSB are both LOW.
Write: This active LOW signal is used to write the internal registers. Data is latched
into the specified address register on the rising edge of WRB when CSB is LOW.
Select: This active LOW device select has to be enabled during register accesses.
Interrupt: This active LOW open drain output transitions LOW when an unmasked
interrupt source is active. This output transitions HIGH when the appropriate register
has been read. This interrupt signals the most critical error states of the device includ-
ing Loss of Pointer, Line Alarm Indication Signal (LAIS), Line Far End Receive Failure
(LFERF), Loss of Frame (LOF), Out of Frame (OOF), Loss of Signal (LOS), and many
others.
Carrier Detect: This differential input controls the recovery function of the Receive PLL
and can be driven by the carrier detect output from optical modules or from external
transition detection circuitry. When this input is at a Logic Low, the input data stream
(RXD±) is recovered normally by the Receive Clock Recovery PLL. When this input is
at a Logic High, the Receive PLL no longer aligns to RXD±, but instead aligns with the
RRCLK * 8 frequency and the LOS alarm register (RDOOLV) will be set. Besides
differential PECL, the ALOS− input can be set to accept single ended PECL input if
ALOS+ is tied to GND. ALOS− has to be decoupled.
Reset: This active LOW signal provides a device reset. This line can be pulled LOW
to put the CY7C955 into the power-down mode. RSTB has an integrated pull-up resis-
tor.
Factory test pin. Must be LOW for normal operation. VCLK has an integrated pull-down
resistor.
Transmit Power
Name
Pin No
TXVDD
12
I/O
Power
TAVD1
4
TAVD2
6
TAVD3
8
TVDDO 18
Power
Power
Power
Power
Description
The Transmit Pad Power supplies the TXD± outputs. TXVDD is physically isolated from
the other device power pins and should be well regulated +5V DC and noise-free for good
performance when driving category 5 unshielded twist pair cabling.
The power pin for the transmit clock synthesizer reference circuitry. TAVD1 should be
connected to analog +5V.
The power pin for the transmit clock synthesizer oscillator. TAVD2 should be connected
to analog +5V.
The power pin for the transmit PECL inputs. TAVD3 should be connected to analog +5V.
Power for TXC± and RXDO±.
5
Share Link: 